Wafer Trimming for Thinned IC Edge Integrity

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Solution Overview

Problem

The existing integrated circuit packaging technologies face challenges in producing thinner ICs without edge chipping and cracking, which reduces manufacturing yield and increases costs due to the limitations of backgrinding processes.

Innovation Solution

The solution involves forming a trimmed edge on the integrated circuit wafer using a trimming process that eliminates sharp edges and stress during backgrinding, applying a thinning process, and using a fill material to prevent damage and improve surface quality, while also utilizing notch trimming to reduce stress on the wafer notch region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If backgrinding process is applied to thin the semiconductor wafer, then IC thickness is reduced, but edge chipping and cracking occur reducing manufacturing yield

Engineering Contradiction:
ImproveIC thicknessVSAvoidedge quality
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The wafer is pre-trimmed before backgrinding to remove sharp edges and reduce stress concentration. This preliminary action prevents edge chipping and cracking during the subsequent thinning process, allowing the wafer to be ground thinner without damaging the ICs at the periphery

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The trimming process applies a counter-action to the stress that will be generated during backgrinding. By removing material from the edges beforehand and creating a relief groove, the process anticipates and prevents the harmful stress concentration that would otherwise cause cracking during thinning

Inventive Principle:
Principle #9Preliminary anti-action

2Length of moving object

If wafer is ground thinner to produce thinner ICs, then IC thickness is reduced, but manufacturing yield decreases due to edge damage

Engineering Contradiction:
ImproveIC thicknessVSAvoidmanufacturing yield
Core Design Contradiction:
Length of moving objectVSProductivity

Solution Approach 1:

Edge trimming is performed as a preliminary step before backgrinding to prevent damage to ICs at the wafer periphery. This ensures that when the wafer is thinned, the ICs remain intact and can be successfully separated and packaged, thereby maintaining high manufacturing yield

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The trimming process selectively removes material from specific regions (edges and relief grooves) where stress concentration occurs, while preserving the quality of the IC regions. This localized treatment prevents damage without affecting the overall thinning process or IC functionality

Inventive Principle:
Principle #3Local quality

3Length of moving object

If backgrinding is applied to achieve thinner ICs, then IC thickness is reduced, but cracking occurs reducing reliability

Engineering Contradiction:
ImproveIC thicknessVSAvoidwafer integrity
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The wafer undergoes preliminary trimming to remove sharp edges and create a relief groove before backgrinding. This pre-treatment reduces stress concentration points that would otherwise lead to cracking during the thinning process, ensuring wafer integrity is maintained throughout manufacturing

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The trimming process applies a counter-action to the stress that will be generated during backgrinding by removing material from critical stress zones beforehand. This prevents the development of cracks that would compromise wafer integrity and IC reliability

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS7786551B2Integrated circuit system with wafer trimming
Publication Date: 2010.08.31 STATS CHIPPAC MANAGEMENT PTE LTD
  • US7786551B2 patent drawing
  • US7786551B2 patent drawing
  • US7786551B2 patent drawing

AI summary

An integrated circuit system includes an integrated circuit wafer, forming a trimmed edge on the integrated circuit wafer, and applying a thinning process on the integrated circuit wafer with the trimmed edge.