Wafer Unit Testing Semiconductor Chips Reducing Fail Memory
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Solution Overview
Problem
Existing test systems for semiconductor wafers face challenges in implementing multiple BIST circuits on printed circuit boards, which reduces the area available for operational circuits and complicates the testing of densely packed semiconductor chips.
Innovation Solution
A test wafer unit with a shape corresponding to the semiconductor wafer, featuring multiple test circuits that can simultaneously test two or more semiconductor chips, connected via a control apparatus to reduce the need for extensive fail memory and allow high-density circuit formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple BIST circuits are mounted on a probe card using a printed circuit board, then testing capability for multiple semiconductor chips is improved, but the area available for operational circuits in each semiconductor chip is reduced
Solution Approach 1:
The invention divides the test circuit functionality into separate modules: BIST circuits remain in the semiconductor chip while control and coordination functions are moved to a controller unit. This segmentation allows the semiconductor chip to maintain full area for operational circuits while the probe card provides the necessary test functionality through distributed control.
Solution Approach 2:
The invention introduces a controller unit as an intermediary between the probe card and semiconductor chips. This controller coordinates the BIST circuits and manages test operations without requiring additional BIST circuitry in each chip, thereby preserving chip area while enabling comprehensive testing capability.
2Productivity
If BIST circuits are provided in semiconductor chips, then testing functionality is improved, but the region for forming actually operating circuits is reduced
Solution Approach 1:
The invention extracts the control and coordination functions from the semiconductor chip and places them in an external controller unit. This allows BIST circuits to remain in the chip for testing purposes while removing the burden of additional control logic, thereby preserving maximum area for operational circuits.
Solution Approach 2:
The controller unit serves multiple functions: it controls BIST circuits across multiple chips, coordinates test sequences, and manages data collection. This universal controller eliminates the need for duplicate control functionality in each chip, preserving area while enhancing testing capability.
3Productivity
If mounting density of semiconductor chips is increased, then productivity is improved, but the area for mounting test circuits decreases
Solution Approach 1:
The invention moves test control functionality from the two-dimensional plane of the semiconductor chip to the probe card dimension. By placing control circuits on the probe card rather than in each chip, the system enables high-density chip mounting while maintaining adequate space for test functionality through vertical/external placement.
Data Source
AI summary
Provided is a test wafer unit for testing a plurality of semiconductor chips formed on a semiconductor wafer, the test wafer unit including: a test wafer having a shape corresponding to a shape of the semiconductor wafer; and a plurality of test circuits formed on the test wafer, each test circuit provided to correspond to two or more of the plurality of semiconductor chips and testing the two or more semiconductor chips. The test wafer unit may include a plurality of connection terminals formed on the test wafer in one to one relation with test terminals of the plurality of semiconductor chips, where each of the plurality of connection terminals is connected to a corresponding one of the test terminals.