Wafer Verification Structures for Layer-Specific Deviation Detection
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Solution Overview
Problem
Existing wafer fabrication processes are vulnerable to malicious modifications during the manufacturing process, making it difficult to detect design deviations and authenticate the authenticity of wafers, which can compromise the functionality and integrity of electronic circuits.
Innovation Solution
A wafer verification system that performs layer-specific inspections by comparing images and physical measurements of fabrication layers to reference data, using unique verification structures as fingerprints to authenticate wafers and detect any deviations from predetermined specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional wafer fabrication processes are used, then manufacturing simplicity is maintained, but vulnerability to malicious modifications increases and detection capability decreases
Solution Approach 1:
The patent embeds verification structures (test targets, fiducial markers) into the wafer during the fabrication process itself, before the wafer is completed. These structures are pre-positioned at specific locations and layers, enabling future verification without adding complex external inspection equipment. The verification data is captured and stored during fabrication, creating a baseline for later authentication.
Solution Approach 2:
The patent introduces verification structures as intermediary elements between the fabrication process and the verification process. These structures (test targets, markers) serve as mediators that carry verification information through multiple fabrication stages and enable authentication by comparing physical measurements against stored reference data, without requiring direct inspection of the actual circuit patterns.
2Measurement precision
If comprehensive inspection methods are implemented, then detection precision improves, but measurement time increases
Solution Approach 1:
The patent extracts verification functions from the main circuit patterns by implementing separate, dedicated verification structures (test targets, fiducial markers) that are distinct from the actual electronic circuits. These verification structures are measured and inspected independently, allowing rapid authentication without requiring comprehensive inspection of all circuit elements, thus reducing inspection time while maintaining detection precision for critical verification points.
Solution Approach 2:
The patent implements verification at strategically selected locations and layers rather than exhaustive inspection of the entire wafer. By measuring verification structures at key fabrication stages and comparing them against stored reference data, the system achieves sufficient detection precision for authentication purposes without the time cost of complete wafer inspection, applying partial action where it provides maximum verification value.
3Measurement precision
If multiple measurement techniques are used, then detection accuracy improves, but process complexity increases
Solution Approach 1:
The patent implements a universal verification structure design that can be measured using multiple different techniques (optical microscopy, electron microscopy, profilometry, etc.). The same test targets and fiducial markers serve multiple verification functions across different measurement modalities, allowing the system to leverage various measurement techniques without requiring separate verification structures for each method, thus managing complexity while maintaining detection accuracy.
Data Source
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AI summary
A method includes obtaining a first reference image of a first wafer. The method includes obtaining a first image of the first wafer in a fabrication state. The first wafer has a first verification structure. The method includes obtaining, when the first wafer is in the fabrication state, a first physical measurement. The first physical measurement corresponds to the first verification structure. The method includes determining that the first image matches the first reference image. The method includes obtaining an electrical parameter measurement corresponding to a verification structure of a received wafer in a post-fabrication state. The method includes calculating a physical parameter value based on the electrical parameter measurement. The method includes generating a verification response by comparing the physical parameter value to the first physical measurement.