Semiconductor Wafer Via Structure for Low-Resistance Backside Contacts
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Solution Overview
Problem
Conventional semiconductor device fabrication methods result in high contact resistance and aluminum spiking due to morphological inconsistency and differing etching rates during the formation of backside metal grid and via structures, leading to inefficient bias voltage application in semiconductor devices like BSI-CIS and depth sensors.
Innovation Solution
The method involves forming a semiconductor device with a trench isolation ring, a first insulating dielectric layer having separate through holes that expose the metal layer and the wafer surface, and a barrier layer to prevent sputtering and ensure direct contact, thereby avoiding over-etching issues and maintaining structural consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If an over-etching process is employed to completely remove the buffer oxide layer, then the through holes can expose both the trench isolation ring and silicon substrate, but this causes high morphological inconsistency at the bottom surfaces of the through holes
Solution Approach 1:
The invention divides the through hole structure into two types: first through holes that expose only the trench isolation ring, and second through holes that expose only the silicon substrate. This segmentation allows each type of through hole to have optimized bottom surface morphology suitable for its specific function, avoiding the morphological inconsistency caused by over-etching in conventional single-type through holes.
2Manufacturing precision
If an over-etching process is used to remove the buffer oxide layer, then the through holes can be formed to expose underlying structures, but this causes sputtering of metal material onto the silicon substrate surface
Solution Approach 1:
The invention segments the through holes into first through holes (exposing trench isolation ring) and second through holes (exposing silicon substrate). This segmentation prevents metal sputtering onto the silicon substrate because the first through holes are positioned such that metal etching does not directly bombard the silicon substrate surface, eliminating the harmful sputtering effect while still achieving complete oxide layer removal.
3Reliability
If the second barrier layer is formed after metal sputtering occurs, then the barrier layer cannot directly contact the silicon substrate, but this leads to significant contact resistance
Solution Approach 1:
The invention creates separate first and second through holes with distinct exposure targets. The second through holes expose the silicon substrate directly, allowing the second barrier layer to form continuous, direct contact with the silicon substrate without interruption from sputtered metal layers. This segmentation ensures both barrier layer continuity and low contact resistance are achieved simultaneously.
4Adaptability or versatility
If through holes are formed to expose both trench isolation ring and silicon substrate, then the structure can support BMG and BMV formation, but this requires a very complicated process
Solution Approach 1:
The invention simplifies the fabrication process by segmenting the through hole formation into two distinct types with different etching conditions and purposes. First through holes are optimized for exposing the trench isolation ring, while second through holes are optimized for exposing the silicon substrate. This segmentation allows each type to be formed with tailored process parameters, reducing overall process complexity while maintaining full structural functionality for both BMG and BMV formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance, prevents aluminum spiking, and enhances the robustness and performance of semiconductor devices by ensuring continuous barrier layers and direct metal-substrate contact, improving the overall fabrication process.
Implementation Method 1
When the over-etching process is a dry etching process, an exposed first metal material layer will also be bombarded
Implementation Method 2
an exposed first metal material layer will also be bombarded, sputtering the metal from the first metal material layer onto the 'clean' surface of the silicon substrate
Data Source
AI summary
A semiconductor device includes a first wafer; a trench isolation ring formed in the first wafer and comprising a first metal layer; a first insulating dielectric layer formed on a surface of the first wafer, including at least one first through hole and at least one second through hole formed therein, the first through hole exposing a surface of the first metal layer, the second through hole exposing the surface of the first wafer; a barrier layer formed at least on the surface of the first wafer exposed in the second through hole; and a second metal layer formed on the first insulating dielectric layer so as to fill up the first and second through holes. The semiconductor device circumvent increased contact resistance, possible aluminum spiking and other problems. The method exhibits improved robustness and imparts higher performance to a semiconductor device fabricated using the method.