Wafer Via Electrode Exposure via Plasma Etching

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Solution Overview

Problem

The high manufacturing cost of device chips with via electrodes is due to the complex processing steps, particularly the costly chemical mechanical polishing (CMP) step required to expose these electrodes.

Innovation Solution

A method that involves grinding and plasma etching to protrude via electrodes from the wafer's reverse side without exposing the insulating films, followed by forming a resist film and plasma etching to remove the insulating films, thereby simplifying the process and eliminating the need for CMP.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If CMP process is used to expose via electrodes, then via electrodes can be exposed on wafer reverse side, but manufacturing cost increases significantly

Engineering Contradiction:
Improvevia electrode exposure precisionVSAvoidmanufacturing cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent replaces the mechanical CMP (chemical mechanical polishing) process with a plasma etching process to expose via electrodes. The plasma etching method uses chemical reactions in a plasma environment to selectively remove material and expose the via electrodes, thereby eliminating the need for costly CMP equipment and processes while achieving the same exposure objective.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the processing parameters by switching from mechanical polishing to plasma-based chemical etching. This involves changing the physical and chemical state of the etching process, using plasma chemistry to achieve selective removal of insulating films and exposure of via electrodes at lower cost.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If multiple processing steps including CMP are used, then via electrodes are properly exposed, but process complexity increases

Engineering Contradiction:
Improvevia electrode exposureVSAvoidprocessing steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent extracts and removes the CMP step from the processing sequence, retaining only the essential plasma etching step to expose via electrodes. This simplification maintains the necessary precision for via electrode exposure while eliminating unnecessary complex processing steps.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

By substituting plasma etching for CMP, the patent reduces process complexity as plasma etching can be integrated more easily into existing semiconductor fabrication lines and requires fewer specialized mechanical polishing steps.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method reduces manufacturing costs by simplifying the processing steps and eliminating the costly CMP process, allowing for cost-effective production of device chips with exposed via electrodes.

Implementation Method 1

supplying a first etching gas turned to a plasma to the reverse side of the wafer, thereby protruding the via electrodes covered with the first insulating films from the reverse side of the wafer

Methodology Applied
Scientific EffectPlasma: Plasma

Implementation Method 2

supplying a second etching gas turned to a plasma to the reverse side of the wafer to remove regions of the first insulating films and the second insulating films underlying the openings

Methodology Applied
Scientific EffectPlasma: Plasma

Data Source

PatentUS10957542B2Method of processing wafer
Publication Date: 2021.03.23 DISCO CORP
  • US10957542B2 patent drawing
  • US10957542B2 patent drawing
  • US10957542B2 patent drawing

AI summary

A method of processing a wafer includes a grinding step of grinding a reverse side of a wafer that has first insulating films covering via electrodes, an electrode protruding step of protruding the via electrodes covered with the first insulating films from the reverse side by supplying a first etching gas turned to a plasma, an insulating film forming step of covering the reverse side with a second insulating film, a via electrode exposing step of supplying a second etching gas turned to a plasma to expose the via electrodes after having formed a resist film having openings overlapping the via electrodes, and an electrode forming step of forming electrodes connected to the via electrodes.