Wafer Voltage Regulators for Test Circuit Power Management
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Solution Overview
Problem
Current semiconductor wafer testing systems face challenges in managing power for test circuits due to uncontrolled resistance variations, leading to voltage degradation and inefficiencies in measuring multiple circuits simultaneously, which results in increased costs and potential damage to SMUs.
Innovation Solution
The integration of voltage regulators within scribe lines on semiconductor wafers, connected to multiple chips, along with selection circuitry that governs access to each chip, allows for precise power management and simultaneous measurement of multiple circuits by using differential amplifiers and pMOS transistors to maintain constant voltage output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SMU voltages are connected through wire connections to the test circuit, then the test circuit can be powered and tested, but the voltage at circuit terminals degrades due to uncontrolled resistance variations
Solution Approach 1:
The patent implements a feedback mechanism where the sense voltage is fed back to adjust the force voltage dynamically. The system continuously monitors the actual voltage at the circuit terminals through the high-impedance sense connection and adjusts the force voltage to compensate for IR drops, ensuring stable and accurate voltage delivery despite resistance variations in the test circuit.
Solution Approach 2:
The patent introduces an intermediary sense connection that acts as a high-impedance voltage monitor between the SMU and the test circuit. This sense connection measures the actual voltage at the circuit terminals without significantly loading the circuit, allowing the system to detect and compensate for voltage drops caused by resistance variations.
2Measurement precision
If two connections (Force and Sense) are used for each SMU to mitigate IR voltage drop, then voltage compensation is improved, but the number of required SMUs and pads increases proportionally for measuring multiple circuits
Solution Approach 1:
The patent makes the Sense connection universal by allowing a single Sense connection to serve multiple Force connections. The high-impedance sense node can monitor voltages for multiple circuits simultaneously, and the system can selectively enable different Force-Sense pairs as needed, reducing the total number of SMUs and pads required compared to dedicated pairs for each circuit.
Solution Approach 2:
The patent merges multiple Sense connections into a single high-impedance sense node that can measure voltages for multiple circuits. By combining the sensing function across multiple circuits into a shared node, the system reduces the number of required SMUs and pads while maintaining accurate voltage compensation for each individual circuit.
3Reliability
If the total resistance between SMU and Kelvin'd points is too large, then the feedback loop is corrupted and the intended voltage cannot be obtained, but reducing resistance limits the applicability to high-impedance circuits
Solution Approach 1:
The patent makes the system dynamic by continuously adjusting the force voltage based on real-time feedback from the sense voltage. The feedback loop actively compensates for resistance variations by dynamically modifying the output voltage, allowing the system to maintain stability and accuracy across a wide range of circuit impedances rather than being limited to fixed resistance conditions.
Solution Approach 2:
The patent changes the operating parameters of the SMU by adjusting the force voltage in response to sense voltage measurements. This parameter adjustment allows the system to adapt to different circuit impedance conditions, maintaining feedback loop stability for both high and low impedance circuits by dynamically optimizing the voltage delivery parameters.
4Speed
If a hardware feedback loop is used to adjust force voltage according to sense voltage, then voltage compensation is fast and accurate, but the feedback loop can be corrupted by large resistance values causing SMU damage
Solution Approach 1:
The patent introduces the high-impedance sense connection as an intermediary that safely monitors the voltage at the circuit terminals without drawing significant current. This sense intermediary provides feedback information about the actual voltage condition, allowing the system to adjust the force voltage appropriately while protecting the SMU from damage even when dealing with high-resistance circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables accurate and efficient power management for test circuits, allowing for simultaneous measurement of multiple circuits while minimizing resistance errors and SMU damage, thereby improving the overall testing process.
Implementation Method 1
Inside the SMU there is a feedback loop that alters the force voltage to compensate for the IR voltage drop through R1F, R2F and R3F so that the intended voltage is realized at the 'Kelvin'd' node points N1, N2 and N3
Implementation Method 2
Current is supplied at a voltage by the SMU to the test circuit, which means the voltage at nodes N4, N5 and N6 will be degraded from the SMU voltages at respective terminals N1, N2 and N3. The resistances R1-R9 are not well controlled.
Implementation Method 3
The Mi1 pMOS gate voltage is adjusted by the differential amplifier 900 to regulate the voltage output
Data Source
AI summary
An apparatus has a semiconductor wafer hosting rows and columns of chips, where the rows and columns of chips are separated by scribe lines. Voltage regulators are positioned within the scribe lines. Each voltage regulator is connected to one or more chips. Selection circuitry is positioned within the scribe lines. The selection circuitry governs access to a chip being tested.