Wafer Warping Reduction via Compensation Elements
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Solution Overview
Problem
Semiconductor wafers experience warping due to uneven distribution of three-dimensional structures during the manufacturing of integrated circuits, leading to macroscopic stress and curvature differences across the wafer, making conventional handling and processing difficult.
Innovation Solution
The method involves forming compensation elements on the wafer with rotated orientations or transverse to the existing IC structures to improve the uniform distribution of thickness-direction structures, using common process steps for patterning and material deposition to reduce warping without increasing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If integrated circuits with unevenly distributed three-dimensional structures are reproduced across the wafer, then the manufacturing process can proceed with conventional methods, but macroscopic stress and warping occur making handling difficult
Solution Approach 1:
The patent applies preliminary anti-action by introducing compensation elements with opposite stress characteristics before the wafer warping becomes unmanageable. These compensation elements are specifically designed to generate stress that counteracts the warping tendency caused by the uneven distribution of three-dimensional structures in the integrated circuits, thereby maintaining wafer flatness throughout the manufacturing process
Solution Approach 2:
The patent applies local quality by placing compensation elements at specific locations on the wafer where stress compensation is most needed. Rather than uniformly distributing all elements, the compensation elements are strategically positioned to address local stress concentrations caused by the uneven distribution of three-dimensional structures in specific circuit regions
2Stability of the object's composition
If compensation elements are added to reduce warping, then wafer flatness improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies merging by integrating the formation of compensation elements into the existing manufacturing process flow. The compensation elements are formed using the same patterning and material deposition steps already required for the integrated circuits, combining multiple functions into a unified process rather than adding separate standalone steps
Solution Approach 2:
The patent applies universality by designing compensation elements that can be formed using the same manufacturing processes and materials as the integrated circuits themselves. The compensation elements utilize identical patterning techniques and material depositions, making the manufacturing apparatus and processes universal for both functional circuits and stress-compensating structures
3Stability of the object's composition
If compensation elements are added to improve uniformity, then warping reduces, but yield may be affected
Solution Approach 1:
The patent applies segmentation by dividing the wafer surface into functional regions (integrated circuits) and compensation regions (compensation elements). This segmentation allows the compensation elements to be placed in designated areas without interfering with the active circuit regions, maintaining yield by preserving the integrity and functionality of the primary product areas
Data Source
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AI summary
In the case of reproducing across a wafer (20) surface an integrated circuit (10) having non-uniformity in the distribution of 3D structures therein, wafer warpage can be reduced by providing in the same wafer surface compensation elements (30) that likewise extend in the thickness direction of the wafer and are positioned to render the distribution of 3D structures over the whole wafer layout more uniform. The compensation elements (30) may comprise rotated instances of the basic IC (10). The compensation elements (30a) may comprise 3D structures that extend in a direction transverse to a first direction in which the 3D structures of the basic ICs align on the wafer.