Wafer-Scale MEMS Packaging with Spacer and Cap
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Solution Overview
Problem
Current packaging solutions for microelectromechanical systems (MEMS) and optics are costly and lack reliability, as they require specialized manufacturing processes and materials that increase the cost and complexity of packaging, while also being sensitive to mechanical damage and contamination.
Innovation Solution
A waferscale packaging system is developed, which involves forming a wafer, fabricating a device element, creating a waferscale spacer around the element, attaching a waferscale cap to protect the element, attaching a carrier, and molding an encapsulant around the protection structure to provide a hermetically sealed and cost-effective solution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ceramic, metal, plastic lid, silicon cover, or glass is used to protect MEMS devices, then reliability is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent applies wafer-scale packaging technology originally developed for integrated circuits to MEMS devices, making the packaging process universal across different device types. This allows MEMS devices to be packaged using the same cost-effective, high-volume processes as standard ICs, eliminating the need for specialized expensive processes while maintaining protection requirements
Solution Approach 2:
The patent uses standard IC packaging materials and processes (mold compounds, epoxy underfills, wire bonds) that are inexpensive and designed for high-volume disposable packaging rather than reusable expensive protective structures. This dramatically reduces packaging cost while providing adequate protection for the device lifetime
2Reliability
If specialized packaging processes are used for MEMS devices, then protection is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines MEMS device fabrication with standard IC packaging processes in a unified wafer-scale flow. Multiple devices are packaged simultaneously using consolidated processes (molding, underfilling, wire bonding, sealing) rather than individual device handling, achieving both protection and cost reduction through economies of scale
Solution Approach 2:
The patent changes the scale parameter from individual device packaging to wafer-scale packaging, processing thousands of devices simultaneously. This parameter change enables the use of inexpensive high-volume processes while maintaining protection quality, directly addressing the cost-protection contradiction
3Ease of manufacture
If conventional packaging methods are used, then manufacturing cost is reduced, but package height increases
Solution Approach 1:
The patent transitions from traditional three-dimensional stacked packaging to a planar wafer-scale approach where devices are packaged in their original wafer form factor. This dimensional change allows cost-effective processing while minimizing vertical height, as devices remain in the thin wafer plane rather than being stacked vertically
Data Source
AI summary
A waferscale package system is provided forming a protection structure comprises forming a wafer, fabricating a device element on the wafer, forming a waferscale spacer around the device element, and attaching a waferscale cap to the waferscale spacer to cover the device element, attaching a carrier to the protection structure, and molding an encapsulant around the protection structure to the carrier.