Wake-Up Control Circuit for Sequential Power-Gate Activation
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Solution Overview
Problem
Power-gated circuits face challenges in managing current spikes during wake-up processes, leading to reliability issues and increased complexity due to the need for additional circuitry for voltage references and biasing comparator circuits.
Innovation Solution
A wake-up control circuit using a pair of field effect transistors as an analog comparator to monitor voltage and generate a trigger signal, along with latches and transistors configured to sequentially couple the power supply to the gated power rail, eliminating the need for analog circuitry and reducing component count and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional wake-up control circuits use analog circuitry for voltage references and biasing comparator circuits, then the circuit can monitor voltage and generate trigger signals, but the chip size and power consumption increase significantly
Solution Approach 1:
The patent extracts and removes the complex analog circuitry (voltage references, biasing comparator circuits) from the wake-up control circuit, retaining only the essential digital components needed for voltage monitoring and trigger signal generation. This extraction eliminates unnecessary complexity while preserving the core functionality needed for reliable operation.
Solution Approach 2:
The patent replaces analog circuitry with a digital implementation using a digital comparator and state machine. This substitution transitions from continuous analog voltage references and biasing circuits to discrete digital logic elements, significantly reducing chip size and power consumption while maintaining the ability to monitor voltage and generate trigger signals.
2Use of energy by moving object
If power gating is implemented to reduce power consumption, then power requirements are met, but current spikes during wake-up cause reliability problems
Solution Approach 1:
The patent implements a state machine that monitors the gated power rail voltage before fully reactivating the power-gated circuit. By detecting when the voltage reaches a threshold level and generating a trigger signal at the appropriate moment, the circuit prepares for wake-up in advance, ensuring that current spikes are controlled and timing is optimized for reliable operation.
Solution Approach 2:
The patent uses a digital comparator to continuously monitor the gated power rail voltage and feeds this information back to the state machine. This feedback mechanism allows the circuit to detect voltage threshold crossings and generate trigger signals only when appropriate conditions are met, preventing premature wake-up and controlling current spike timing to ensure reliability.
3Adaptability or versatility
If component density is increased to improve device functionality, then more features are integrated, but power dissipation from leakage and increased functionality increases
Solution Approach 1:
The patent segments the power supply into multiple independent gated power rails, each controllable by its own wake-up control circuit. This segmentation allows individual circuits or blocks to be powered down independently when not in use, reducing overall power dissipation from leakage while maintaining the ability to activate only the necessary functional blocks, thus preserving device versatility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces chip size by 90% and power consumption by 80% compared to traditional wake-up control circuits, effectively limiting current spikes and improving device reliability.
Implementation Method 1
The control circuit can include a pair of field effect transistors (FETs) configured as an analog comparator, such as to measure or monitor the voltage on the gated power rail
Data Source
AI summary
A power gating circuit includes a first transistor to couple a power supply to a gated power rail after receiving a control signal. The power gating circuit also includes two or more transistors coupled in parallel with the first switch, the one or more transistors configured to sequentially couple the power supply to the gated power rail according to a sequence determined by a comparator circuit and one or more cascaded latches.