Wakeup Trigger Circuit for Low Power IC Testing
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Solution Overview
Problem
As integrated circuits (ICs) become more complex, the increasing number of I/O pads requiring probe testing during low power mode testing leads to increased test time and cost, necessitating a more efficient method to verify proper operation in low power mode.
Innovation Solution
The implementation of a wakeup trigger generation circuit within the IC that internally generates wakeup signals on I/O pads, reducing the need for external probes and allowing for parallel testing by reusing on-chip resources, such as the pad expose register and multiplexors, to manage trigger signals and detect proper entry and exit from low power mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external probes contact each I/O pad to apply wakeup trigger signals for low power mode testing, then complete low power mode testing coverage is achieved, but test time and test cost increase
Solution Approach 1:
The IC performs low power mode testing on itself by internally generating wakeup trigger signals through the trigger generation circuit, eliminating the need for external probes to contact each I/O pad. The IC's own resources (pad expose register, multiplexors, trigger generation circuit) are utilized to autonomously complete the testing, thereby reducing test time while maintaining complete testing coverage.
Solution Approach 2:
A trigger generation circuit is introduced as an intermediary component that generates internal wakeup trigger signals to replace external probe contacts. This intermediary circuit receives control signals from the pad expose register and produces the necessary trigger signals on selected I/O pads, enabling the IC to test itself without requiring external probe equipment for each pad.
2Reliability
If external probes contact each I/O pad to apply wakeup trigger signals, then proper wakeup functionality is verified, but test cost increases
Solution Approach 1:
The IC autonomously verifies its own wakeup functionality by using internal circuits to generate and apply wakeup trigger signals. The trigger generation circuit, controlled by the pad expose register, produces signals that test each I/O pad's wakeup capability without requiring expensive external probe equipment, thereby reducing test cost while maintaining verification reliability.
Solution Approach 2:
The pad expose register and multiplexors are designed to serve multiple functions: they control normal I/O operations and simultaneously manage low power mode testing by selecting which pads receive internal trigger signals. This multi-functionality eliminates the need for dedicated testing equipment, reducing test cost while maintaining comprehensive wakeup functionality verification.
3Adaptability or versatility
If the number of I/O pads increases to handle IC complexity, then IC functionality improves, but the number of probes required for testing increases
Solution Approach 1:
As IC complexity and the number of I/O pads increase, the trigger generation circuit acts as an intermediary that consolidates the testing function. Instead of requiring one external probe per pad, the trigger generation circuit internally generates signals for multiple pads, reducing the number of external probe contacts needed while maintaining the ability to test all pads for wakeup functionality.
Solution Approach 2:
The IC uses its own internal resources (trigger generation circuit, pad expose register, multiplexors) to perform testing on all I/O pads regardless of the total number of pads. This self-service capability means that adding more pads to increase IC functionality does not proportionally increase the number of external probes required, as the internal circuitry handles the testing autonomously.
Data Source
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AI summary
An integrated circuit includes a plurality of external terminal circuits, each having an external terminal. The integrated circuit includes a wakeup detector including a plurality of inputs. Each input of the plurality of inputs is coupled to an external terminal circuit. The wakeup detector generates an output signal indicative of an external terminal of the plurality of external terminal circuits being placed at a wakeup voltage. The integrated circuit includes a trigger generation circuit having a plurality of outputs in which each output is coupled to an external terminal circuit to generate a wake-up voltage at an external terminal of the external terminal circuit by coupling the external terminal to a power supply terminal of the integrated circuit to generate an indication of the external terminal being at the wakeup voltage at the wakeup detector when at least a portion of the integrated circuit is in a low power mode.