Wall Fin Dielectric Isolation for Dense FinFET and GAA Layouts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increase in parasitic capacitance between adjacent fins in Fin FETs and GAA FETs degrades circuit speed and reduces device performance, while the shape of the epitaxial source/drain structure in these transistors affects the Ion/Ioff current ratio, leading to suboptimal device performance.
Innovation Solution
Employing a wall fin structure with a dielectric dummy fin to physically and electrically separate adjacent source/drain epitaxial layers, defining an optimal shape that improves the Ion/Ioff current ratio and enhances device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If adjacent fins are placed closer together to increase device density, then device density is improved, but parasitic capacitance between adjacent fins increases degrading circuit speed
Solution Approach 1:
A dielectric material is introduced as an intermediary substance between adjacent fin structures. This dielectric layer acts as a mediator that reduces the parasitic capacitance coupling between fins while allowing the fins to remain in close proximity for high device density. The dielectric material with appropriate permittivity properties enables both high density and acceptable circuit speed performance.
Solution Approach 2:
The patent applies different material properties to different regions of the device. Specifically, dielectric materials with tailored permittivity characteristics are applied locally between adjacent fins, while other regions maintain their original structure. This local modification allows optimization of capacitance reduction in critical areas without compromising overall device density and performance.
2Ease of manufacture
If the epitaxial source/drain structure shape is not optimized, then manufacturing is simpler, but the Ion/Ioff current ratio is suboptimal reducing device performance
Solution Approach 1:
The dielectric layer is deposited between the fin structures before the epitaxial growth of source/drain regions. This preliminary action ensures that the dielectric is already in place to define and control the shape of the epitaxial source/drain structures during subsequent growth processes. The pre-positioned dielectric acts as a template that guides epitaxial growth to achieve optimal shapes for high Ion/Ioff ratios.
Solution Approach 2:
The dielectric material serves as an intermediary that defines the interface and shape of the epitaxial source/drain structures. By controlling the dielectric's position and properties, the patent enables precise control over the epitaxial growth morphology, achieving optimal source/drain shapes that maximize the Ion/Ioff current ratio while maintaining manufacturability through standard epitaxial processes.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure is formed. The fin structure includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure, and a hard mask layer over the stacked layer. An isolation insulating layer is formed so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed, and a second dielectric layer made of a different material than the first dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer, thereby forming a wall fin structure.