Wall Fin Dielectric Layers for GAA Short-Channel Control
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Solution Overview
Problem
In three-dimensional semiconductor devices like gate-all-around (GAA) FETs, the bottom part of the channel region is not under close gate control, leading to sub-optimal performance due to less effective depletion and increased short-channel effects as transistor dimensions shrink below 10-15 nm nodes.
Innovation Solution
Employing a wall fin structure with dielectric layers to separate adjacent source/drain epitaxial layers, using a sacrificial cladding layer and dielectric layers to define the shape of the source/drain regions, and forming a gate electrode that surrounds the channel region to enhance control and reduce short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional Fin FET structure is used with gate electrode adjacent to three side surfaces, then the gate structure surrounds the fin on three surfaces providing control, but the bottom part of the channel is far away from the gate electrode resulting in poor gate control and increased short-channel effects
Solution Approach 1:
The patent transitions from a three-sided gate wrap structure to a gate-all-around structure where the gate electrode completely surrounds the channel region in four sides, adding dimensional completeness to the gate control geometry and eliminating the uncovered bottom surface
Solution Approach 2:
The channel region is segmented into multiple thin channel layers stacked vertically, with gate electrodes surrounding each channel layer, enabling fuller depletion and better control over short-channel effects through divided channel structures
2Productivity
If transistor dimensions are scaled down to sub 10-15 nm technology nodes to increase device density, then higher device density and performance are achieved, but fabrication and design challenges increase resulting in sub-optimal performance
Solution Approach 1:
Different material compositions are used for different channel layers (e.g., SiGe, Si, SiC) to optimize local electrical properties and stress characteristics in specific regions, enabling better performance at scaled dimensions while managing fabrication complexity
Solution Approach 2:
The channel structure employs composite material stacks with alternating semiconductor layers of different compositions and properties, combining the advantages of multiple materials to achieve superior electrical characteristics at nanometer scale dimensions
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first and second semiconductor layers and a hard mask layer over the stacked layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. An etching is performed to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer and a second dielectric layer made of a different material than the first dielectric layer are formed. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer. During the etching operation, a protection layer is formed over the sacrificial cladding layer.