Wall Fin Structure for Source/Drain Epitaxy Separation
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Solution Overview
Problem
In the semiconductor industry, particularly for FinFET and GAA FET devices, the shape of the epitaxial source/drain structure significantly impacts device performance, with existing methods failing to effectively separate adjacent source/drain epitaxial layers, leading to suboptimal Ion/Ioff current ratios and device performance.
Innovation Solution
The implementation of a wall fin structure, comprising a dielectric dummy fin, physically and electrically separates adjacent source/drain epitaxial layers, defining their shape and improving the epitaxial source/drain structure through a series of layered formations and etching processes, including the use of sacrificial cladding layers and dielectric layers to form a V-shape trench.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used without wall fin structure, then the manufacturing process is simpler, but adjacent source/drain epitaxial layers cannot be effectively separated leading to poor device performance
Solution Approach 1:
The patent introduces a wall fin structure that physically segments and separates adjacent source/drain epitaxial layers. This segmentation prevents unwanted interaction between adjacent devices and enables independent control of each device's epitaxial growth, directly improving device performance through effective separation.
Solution Approach 2:
The wall fin structure acts as an intermediary element between adjacent source/drain regions. By introducing this intermediate structure, the patent achieves effective separation and control of epitaxial layers without requiring complex process modifications, resolving the contradiction between simplicity and performance.
2Manufacturing precision
If multi-layer dielectric structure with V-shape trench is implemented, then source/drain epitaxial layer shape is optimized, but manufacturing process becomes more complex
Solution Approach 1:
The patent employs preliminary actions by forming sacrificial cladding layers and multi-layer dielectric structures before the actual epitaxial growth process. These preliminary structures guide and define the shape of epitaxial layers, ensuring precise control during growth while maintaining a systematic manufacturing approach.
Solution Approach 2:
The introduction of V-shape trenches and multi-layer dielectric structures adds dimensional complexity to the manufacturing process. By creating structures in multiple dimensions (vertical trenches, layered dielectrics), the patent achieves precise epitaxial layer shape control that cannot be obtained through simple planar processes.
3Reliability
If wall fin structure is formed using multiple dielectric layers and etching processes, then short-channel effects are reduced, but fabrication time and complexity increase
Solution Approach 1:
The patent utilizes parameter changes by employing multiple dielectric layers with different etch selectivities and properties. By changing material parameters (different dielectric materials) and process parameters (etching conditions), the patent achieves effective short-channel effect control through the wall fin structure while managing fabrication complexity.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.