Wall Fin Structure for Gate-All-Around FET Channel Control
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Solution Overview
Problem
As semiconductor technology advances to sub 10-15 nm nodes, gate-all-around (GAA) FETs face challenges in achieving optimal device performance due to issues with short-channel effects and incomplete gate control over the channel region.
Innovation Solution
The implementation of a wall fin structure, comprising multiple dielectric layers with different materials, is used to physically and electrically separate adjacent source/drain epitaxial layers, thereby defining their shape and improving gate control in GAA FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate-all-around (GAA) FET structure is implemented to improve gate control over the channel region, then the transistor performance is enhanced with fuller depletion in the channel, but the manufacturing complexity increases due to the need for precise multi-layer dielectric structures and epitaxial layer formation
Solution Approach 1:
The patent divides the gate structure into multiple segments: a gate electrode surrounded by a gate dielectric layer, with additional dielectric layers (first and second dielectric layers) segmented between adjacent fins. This segmentation allows each layer to perform specific functions - the gate dielectric provides electrical isolation, while the first and second dielectric layers provide mechanical support and electrical isolation, enabling full gate wraparound control without excessive manufacturing complexity
Solution Approach 2:
The patent implements a nested structure where the gate electrode is surrounded by the gate dielectric layer, which is in turn surrounded by the first and second dielectric layers. These layers are nested between adjacent fins, creating a compact multi-layer structure that achieves full gate control while maintaining manufacturability through systematic layer integration
2Productivity
If transistor dimensions are scaled down to sub 10-15 nm technology nodes to increase device density, then higher device density and performance are achieved, but short-channel effects worsen and gate control becomes insufficient
Solution Approach 1:
The patent transitions from planar gate control to three-dimensional gate-all-around control by wrapping the gate electrode completely around the channel region in vertical and lateral dimensions. This dimensional change allows the gate to control the channel from all directions, maintaining effective gate control even as transistor dimensions scale down to sub 10-15 nm nodes and device density increases
3Ease of manufacture
If a Fin FET structure is used with gate adjacent to three side surfaces of the channel, then manufacturing is simplified compared to GAA, but the fourth side (bottom part) is far from the gate electrode resulting in incomplete gate control
Solution Approach 1:
The patent inverts the conventional Fin FET approach by completely wrapping the gate around the channel region instead of leaving the bottom side exposed. The gate electrode surrounds the channel in all directions, and the first and second dielectric layers are positioned to support this inverted structure, ensuring complete gate control while maintaining manufacturing feasibility through systematic layer deposition
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure is formed. The fin structure includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure, and a hard mask layer over the stacked layer. An isolation insulating layer is formed so that the hard mask layer and the stacked layer are exposed from the isolation insulating layer. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed, and a second dielectric layer made of a different material than the first dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer, thereby forming a wall fin structure.