Wall Fin Structure for Better Gate Control in GAA FETs
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Solution Overview
Problem
In three-dimensional semiconductor designs like Fin FET and GAA FET, the bottom part of the channel region is not under close gate control, leading to sub-optimal performance due to issues such as short-channel effects and drain induced barrier lowering, especially as transistor dimensions shrink to sub-10-15 nm nodes.
Innovation Solution
Employing a wall fin structure with a dielectric dummy fin to physically and electrically separate adjacent source/drain epitaxial layers, defining an optimal shape that improves the Ion/Ioff current ratio and device performance by enhancing gate control over the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional designs like Fin FET and GAA FET are used to increase device density and performance, then higher device density and performance are achieved, but the bottom part of the channel region is not under close gate control, leading to short-channel effects and drain induced barrier lowering
Solution Approach 1:
The gate structure is segmented into multiple portions that wrap around the channel region from different directions. Instead of a single planar gate, the gate electrode is divided into segments that can individually control different portions of the channel, including the bottom part that was previously uncontrollable.
Solution Approach 2:
The gate control is extended from a two-dimensional planar configuration to a three-dimensional wrap-around configuration. The gate electrode wraps around the channel region vertically and laterally, adding dimensional control authority over the entire channel surface including the bottom portion.
2Productivity
If transistor dimensions are scaled down to sub-10-15 nm nodes to pursue higher performance, then device performance is improved, but short-channel effects and drain induced barrier lowering become more severe due to reduced gate control
Solution Approach 1:
The gate electrode is segmented into multiple controlled portions that can independently influence different regions of the scaled-down channel. This segmentation allows for more precise electrostatic control at sub-10-15 nm dimensions, counteracting the increased short-channel effects that occur at smaller scales.
Solution Approach 2:
By transitioning to a three-dimensional gate-all-around configuration, the effective gate control area increases proportionally more than the channel dimensions are reduced. This dimensional approach compensates for the severe short-channel effects inherent in scaled transistors.
3Device complexity
If a gate electrode is placed adjacent to three side surfaces of the channel region in Fin FET design, then partial gate control is achieved, but the fourth side (bottom part) remains far from the gate electrode and is not under close gate control
Solution Approach 1:
The gate structure is divided into multiple segments including lateral gates and vertical gates that wrap around the channel. This segmentation enables the gate to extend to and control all four sides of the channel region, including the previously inaccessible bottom surface.
Solution Approach 2:
The gate structure transitions from a planar configuration controlling three sides to a three-dimensional wrap-around configuration that controls all four sides. The gate electrode extends vertically and laterally to encompass the entire channel perimeter, achieving complete surface control.
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure, which includes a stacked layer of first semiconductor layers and second semiconductor layers disposed over a bottom fin structure and a hard mask layer over the stacked layer, is formed. An isolation insulating layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer is formed. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer is recessed. A third dielectric layer is formed on the recessed second dielectric layer. The third dielectric layer is partially removed to form a trench. A fourth dielectric layer is formed by filling the trench with a dielectric material, thereby forming a wall fin structure.