Wallace Tree Compressor Gating for Low-Power Multiplier Circuits
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Solution Overview
Problem
Existing compressors in multiplier circuits exhibit high power consumption and delay, particularly in small numerical operations.
Innovation Solution
A compressor circuit design incorporating a first and second full adder, along with selection circuits to control the operation of the second full adder based on input signals, ensuring it is turned off when not needed to reduce energy consumption and delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional multiplier circuit is used, then the circuit structure is simple, but the multiplication speed is slow and power consumption is high
Solution Approach 1:
The multiplier circuit is divided into multiple processing stages (first processing stage, second processing stage, third processing stage) that operate in parallel. Each stage handles specific bit combinations of the multiplication operation simultaneously, rather than sequentially, thereby achieving faster multiplication speed while maintaining reasonable circuit complexity through structured division of labor.
2Use of energy by moving object
If a conventional multiplier circuit is used, then the circuit structure is simple, but the power consumption is high
Solution Approach 1:
The processing stages are segmented such that not all circuit elements need to operate at full power simultaneously. The first processing stage handles significant bit combinations while subsequent stages handle less significant bits, allowing for progressive power reduction across stages and overall lower power consumption compared to conventional circuits.
Solution Approach 2:
The circuit performs partial multiplication operations in each stage, where the first processing stage performs the most critical multiplications and later stages complete the remaining operations. This partial action approach reduces the peak power consumption by distributing the computational load rather than requiring all elements to operate at maximum capacity simultaneously.
3Speed
If processing stages are added to improve multiplication speed, then the multiplication speed increases, but the circuit area increases
Solution Approach 1:
Multiple processing stages are merged into a single integrated circuit structure where intermediate results from the first processing stage are directly fed into the second processing stage without requiring separate physical modules. This merging approach achieves fast parallel processing while minimizing the overall circuit area by eliminating redundant interfaces and connection elements between stages.
Solution Approach 2:
The processing stages are arranged in a hierarchical structure where the first processing stage handles more significant bits and subsequent stages handle less significant bits in a cascading manner. This dimensional organization of computational tasks allows efficient space utilization by packing stages closely together with direct signal routing, reducing the overall circuit footprint while maintaining parallel processing speed.
Data Source
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AI summary
The present disclosure provides a compressor circuit, a Wallace tree circuit, a multiplier circuit, a chip and an apparatus. The compressor circuit includes a first full adder, a second full adder, and a first selection circuit. An output end of the first full adder is connected to an input end of the first selection circuit, and an output end of the first selection circuit is connected to an input end of the second full adder. The first selection circuit is configured to determine an input signal output by the first selection circuit to the second full adder according to a first selection signal; and the input signal output by the first selection circuit to the second full adder and a most significant bit signal of a plurality of input signals of the compressor circuit are used to control turning on and turning off of the second full adder, which can reduce circuit power consumption and delay.