Warp-Level Work Queue Coalescing for GPU-NIC Concurrency
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Solution Overview
Problem
Conventional communication protocols in high-performance computing systems face challenges in optimizing latency and memory consumption, particularly when using GPUs for kernel-initiated communications, which can lead to inefficiencies and performance bottlenecks.
Innovation Solution
The proposed solution involves improving communication efficiencies by implementing warp-level coalescing of work queue element (WQE) slot reservations and creations, as well as coalescing memory barriers and doorbell updates, to enhance parallelism and reduce memory barriers and locking scope.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional WQE submission algorithms are used with GPU, then the GPU can submit work to NIC, but locking the network QP limits concurrency and creating one QP per thread consumes hundreds GB of GPU memory
Solution Approach 1:
Multiple threads within a warp share a single queue pair (QP) for submitting work queue elements (WQEs) to the NIC. Instead of each thread having its own QP, the patent merges the submission capability of multiple threads into a shared QP, allowing concurrent access without requiring proportional memory resources. This is achieved through atomic operations on the queue head pointer and coordinated doorbell updates.
Solution Approach 2:
The submission process is segmented into distinct phases: (1) atomic update of queue head pointer to reserve WQE slots, (2) parallel creation of WQEs by multiple threads, and (3) coordinated doorbell update to notify NIC. This segmentation allows threads to work in parallel on WQE creation while only critical synchronization points require coordination, improving concurrency without increasing memory consumption.
2Productivity
If traditional WQE submission is used, then work can be submitted to NIC, but each WQE submission requires issuing a memory barrier which incurs significant latency for GPU SMS
Solution Approach 1:
Multiple WQE submissions that would traditionally require separate memory barriers are merged into a single coordinated submission. The patent combines the doorbell updates from multiple threads into one atomic operation, and uses a single memory barrier to ensure visibility of all WQE writes to the NIC, dramatically reducing the frequency and overhead of memory barrier operations.
Solution Approach 2:
The queue head pointer is atomically updated before threads create their WQEs, pre-reserving slots in the work queue. This preliminary action ensures that subsequent WQE writes by multiple threads do not require additional synchronization or memory barriers, as the target locations are already allocated and validated.
3Reliability
If locking is used to protect shared QP access, then data consistency is maintained, but concurrency is limited and performance is reduced
Solution Approach 1:
The patent extracts the critical synchronization requirement from the entire WQE submission process and concentrates it into a single atomic operation on the queue head pointer. Once the pointer is atomically updated and slots are reserved, threads can freely write their WQEs without any locking, as the target locations are already allocated. This extraction of synchronization to a minimal critical section maintains data consistency while maximizing concurrency.
Solution Approach 2:
The queue head pointer serves as an intermediary that coordinates access to the shared work queue without requiring continuous locking. The atomic update of this pointer acts as a mediator that establishes ownership of WQE slots, allowing subsequent writes by multiple threads to proceed independently and concurrently without conflict or locking overhead.
Data Source
AI summary
A system is described having an input/output (IO) device and a processing unit coupled with the IO device. The processing unit is enabled to elect a thread from among a plurality of threads to atomically update a queue head pointer, uses the queue head pointer to reserve space in a plurality of memory registers for work queue elements belonging to the plurality of threads, and submit the work queue elements to the IO device.