Warpage Control Layer for Microelectronics Packages
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Solution Overview
Problem
Conventional techniques for reducing warpage in microelectronic packages either increase the z-height or introduce complex processing challenges, especially when using coreless substrates, which can exacerbate warpage issues and increase costs.
Innovation Solution
A warpage control layer or stiffener is attached to the bottom surface of the microelectronic package substrate, matching the coefficient of thermal expansion of the die and having a thickness similar to the die, which is positioned between the package and the motherboard to control warpage without increasing the z-height, using materials like insulating or metallic materials with copper pillar segments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If core material is added to the organic substrate to reduce CTE, then warpage is reduced, but z-height significantly increases
Solution Approach 1:
A thin stiffener layer is introduced as an intermediary element between the organic substrate and the die. This stiffener has a thickness of about 1-10 micrometers, which is sufficient to provide mechanical support and control warpage without significantly increasing the overall z-height of the package. The stiffener acts as a mediator that balances the CTE mismatch between components.
Solution Approach 2:
The patent changes the thickness parameter of the stiffener layer to be very thin (1-10 micrometers) compared to conventional thick core materials. This parameter change allows the stiffener to provide adequate mechanical support for warpage control while minimizing its contribution to the overall package height.
2Manufacturing precision
If a metal stiffener or organic substrate interposer is added on top of the die, then warpage is reduced, but z-height significantly increases and processing complexity increases
Solution Approach 1:
The stiffener is positioned as an intermediary layer between the organic substrate and the die, rather than adding components on top of the die. This positioning simplifies the processing sequence by eliminating the need for additional attachment steps on the die surface and reduces the number of interfaces that need to be managed.
Solution Approach 2:
The stiffener layer is combined with the organic substrate to form a unified support structure. This merging of functions allows the stiffener to work in conjunction with the substrate to control warpage, reducing the need for separate complex processing steps for attaching and managing additional layers on the die.
3Length of moving object
If coreless substrate is used to reduce z-height, then z-height is reduced, but warpage increases
Solution Approach 1:
Instead of using a thick core material throughout the entire substrate (which would increase z-height), the patent applies a thin stiffener layer only in the local region where mechanical support is needed. This local quality approach provides warpage control where necessary while maintaining the low z-height benefit of the coreless substrate in other areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces warpage across a wide range of temperatures, maintains a low z-height, simplifies the assembly process, and provides improved mechanical balance, while allowing for flexibility in design choices and PoP architecture without adding complexity or height.
Implementation Method 1
A warpage control layer or stiffener is attached to the bottom surface of the microelectronic package substrate, matching the coefficient of thermal expansion of the die
Data Source
AI summary
Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.