Multi-Core Watchdog Arbitration via Time-Slot Segmentation
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Solution Overview
Problem
In systems with multiple processor cores, overlapping notifications to a watchdog timer (WDT) can lead to contention, causing the WDT to incorrectly recognize normal operation and initiate unnecessary resets.
Innovation Solution
A control apparatus with multiple processor cores that periodically update information in memory about their normal operation, where a first processor core monitors these updates to prevent contention by determining if notifications have been received correctly and controlling the WDT accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple processor cores share a common watchdog timer and send notifications simultaneously, then system monitoring coverage is improved, but notification contention occurs causing incorrect malfunction recognition
Solution Approach 1:
The patent divides the notification process into separate time slots for each processor core. The arbitration unit allocates distinct notification periods to different cores, preventing simultaneous access to the watchdog timer. This segmentation of the notification timeline eliminates contention while maintaining comprehensive monitoring coverage across all cores.
Solution Approach 2:
The patent introduces an arbitration unit as an intermediary between multiple processor cores and the watchdog timer. This mediator manages notification requests from different cores, sequencing them to prevent overlap. The arbitration unit acts as a buffer that coordinates access timing, ensuring each core's notification reaches the watchdog timer without conflict, thereby preventing incorrect malfunction detection.
2Productivity
If multiple processor cores send notifications to the watchdog timer simultaneously, then monitoring efficiency is improved, but contention causes unnecessary system resets
Solution Approach 1:
The patent implements preliminary arbitration of notification requests before they reach the watchdog timer. The arbitration unit pre-sequences notification timing for each processor core, establishing an ordered access pattern in advance. This preliminary organization of notification timing prevents contention at the watchdog timer interface, eliminating unnecessary resets while preserving efficient monitoring of all cores.
Data Source
AI summary
A control apparatus includes multiple processor cores connected to: a monitor that monitors whether a first processor core, the first processor core being any processor core among the multiple processor cores, is operating normally; and a memory having multiple storage areas pre-associated with each of the multiple processor cores. Each of the multiple processor cores periodically writes and updates information to the corresponding storage area in the memory, the information indicating that each of the processor cores is operating normally, and the first processor core determines whether the information in each of the storage areas in the memory has been updated by each of the multiple processor cores, and controls the monitor on the basis of a result of the determination.