Watchdog BIT Reset Inhibit Circuit for Fast System Readiness
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Solution Overview
Problem
In aerospace applications, watchdog circuits used in embedded systems face challenges in performing diagnostic tests without disrupting normal operations and avoiding false reset conditions, which can impact system readiness time and reliability.
Innovation Solution
A watchdog circuit with an active integrated reset circuit and a built-in test reset inhibit circuit that prevents processor resets during diagnostic tests, using a supervisor block timer and enable signals to inhibit resets, ensuring system stability and reducing false triggers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diagnostic tests (BIT) are incorporated to check hardware health, then system reliability is improved, but system readiness time increases
Solution Approach 1:
The supervisor block timer is pre-configured with a predetermined time value that is loaded before the BIT sequence starts. This preliminary setup allows the timer to immediately begin counting when enabled, without requiring configuration during the test execution, thereby minimizing the time added to system readiness.
Solution Approach 2:
The WD BIT reset inhibit circuit acts as an intermediary between the active watchdog integrated reset circuit and the processor reset input. This intermediary component selectively blocks reset signals during BIT execution based on the supervisor block timer status, allowing diagnostic tests to proceed without causing false processor resets while maintaining the watchdog's normal protective function.
2Reliability
If BIT is executed to diagnose watchdog circuit health, then diagnostic capability is improved, but false reset conditions may occur
Solution Approach 1:
The WD BIT reset inhibit circuit serves as a protective intermediary that selectively blocks reset signals from reaching the processor during BIT execution. The circuit monitors the supervisor block timer status and only inhibits resets when the timer indicates BIT is in progress, thereby preventing false reset conditions while allowing legitimate watchdog resets to function normally outside the test period.
Solution Approach 2:
The reset inhibit circuit is pre-configured to recognize and counteract the potential harmful effect of false resets during BIT. By having the supervisor block timer pre-loaded with the appropriate time value and the inhibit circuit pre-configured to respond to its status, the system proactively prevents false resets before they can occur during diagnostic testing.
3Reliability
If watchdog circuit performs reset function, then processor protection is improved, but system stability during BIT is reduced
Solution Approach 1:
The reset inhibit function is dynamically controlled based on the supervisor block timer status. The WD BIT reset inhibit circuit actively monitors whether the timer has expired and adjusts its behavior accordingly - blocking resets when BIT is in progress (timer not expired) and allowing resets when BIT is complete (timer expired). This dynamic adaptation maintains system stability during testing while preserving watchdog protection capabilities.
Solution Approach 2:
The WD BIT reset inhibit circuit acts as a dynamic intermediary that modulates the watchdog reset signal based on BIT status. It transparently allows normal watchdog operation during regular system execution while selectively blocking reset signals only during the configured BIT time window, thereby maintaining both processor protection and system stability during diagnostics.
Data Source
AI summary
A method of performing a built in test on a watchdog circuit including a watchdog timer includes: initiating the built in test with a processor being monitored by the watchdog circuit, wherein initiating includes enabling a watchdog circuit built in test reset inhibit circuit (WD BIT reset inhibit circuit) connected between an output of an active watchdog integrated reset circuit connected to the processor and a reset input of the processor; and ceasing to provide a strobe signal to the active watchdog integrated reset circuit that resets a watchdog counter in the active watchdog integrated reset circuit, the active watchdog integrated reset circuit causing a reset of the processor via its output when the watchdog counter expires by providing a signal to a reset input of the processor.