Two-Stage Watchdog Chaining for BMC Debug Recovery
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Solution Overview
Problem
Not all computing systems, such as those using Aspeed baseboard management controller (BMC) chips, support two-stage watchdogs, limiting their ability to prioritize GPIO interrupts for watchdog triggers and thus preventing effective debug information collection and system recovery.
Innovation Solution
Hardware chaining of an internal and external watchdog is implemented, where the expiry of the internal watchdog triggers a high-priority interrupt for debug information collection and initiates a secondary watchdog timer, ensuring system reset if the first stage fails to recover gracefully.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardware chaining of internal and external watchdog is implemented, then debug information collection and system recovery capability are improved, but device complexity increases
Solution Approach 1:
The patent combines an internal watchdog timer and an external watchdog timer into a chained two-stage watchdog system. The internal watchdog triggers the external watchdog, creating a coordinated recovery mechanism that leverages both internal fast interrupt capability and external reset capability to achieve reliable system recovery while managing complexity through functional integration.
2Ease of operation
If all GPIO interrupts are configured as interrupts or fast interrupts with same priority, then ease of operation is improved, but ability to prioritize watchdog triggers is worsened
Solution Approach 1:
The patent makes the watchdog trigger GPIO pin multi-functional by allowing it to serve both as a general-purpose interrupt and as a dedicated watchdog trigger. This universal pin can be configured in different modes (interrupt or fast interrupt) while the watchdog function is layered on top, enabling prioritization without requiring separate dedicated hardware pins for each function.
Data Source
AI summary
According to some embodiments, a system comprises a computer system comprising a processing unit, an interrupt controller, an internal watchdog, and a computer system reset interface. The system further comprises a watchdog controller comprising a secondary watchdog timer. Expiry of the computer system internal watchdog triggers the interrupt controller to cause the processing unit to collect debug information and triggers the watchdog controller to start a secondary watchdog timer. Expiry of the secondary watchdog timer triggers the watchdog controller to reset the computer system.