Always-On Watchdog Reset Circuit for IC Voltage Instability
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Solution Overview
Problem
Existing integrated circuits face system crashes due to voltage instability, with external reset circuits increasing manufacturing costs and internal brown-out detection (BOD) circuits resulting in inaccurate voltage detection due to process variations, leading to a 'dead zone' where low input voltages are not detected.
Innovation Solution
Incorporating a power-on reset (POR) circuit, a watchdog timer, AND gates, and a power management control circuit to generate reset signals and manage output currents, enabling automatic voltage resets without external circuits, thus eliminating the need for manual resets and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external reset circuit is used to resolve voltage instability, then system reliability is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges the reset circuit functionality directly into the integrated circuit chip, combining the POR circuit, watchdog timer, and power management control circuit into a single unified device. This integration eliminates the need for separate external reset circuits while maintaining system reliability for detecting and responding to voltage instability.
2Device complexity
If an internal BOD circuit is used to detect low voltage, then device complexity is reduced, but measurement precision deteriorates due to dead zone
Solution Approach 1:
The patent segments the voltage detection function into multiple independent circuits with different detection thresholds: the POR circuit detects when voltage rises above a first threshold, while the BOD circuit detects when voltage falls below a second threshold. This segmentation eliminates the dead zone problem by ensuring that detection occurs at appropriate voltage levels without overlap gaps.
Solution Approach 2:
The watchdog timer acts as an intermediary component that receives the enabling signal from the BOD circuit and generates periodic timeout signals. This intermediary mechanism ensures that even when voltage fluctuates within the dead zone, the system can still detect instability through the timeout signal generation and trigger appropriate reset actions.
3Ease of operation
If manual reset is required for voltage instability, then ease of operation is reduced, but device complexity is minimized
Solution Approach 1:
The integrated circuit implements self-service through automatic reset functionality. When the power management control circuit detects voltage instability or crashes through the timeout signal mechanism, it automatically triggers a reset without requiring user intervention. This eliminates the need for manual reset operations while maintaining relatively simple device architecture.
Data Source
AI summary
An integrated circuit includes a power-on reset (POR) circuit, a watchdog timer, a first AND gate and a power management control circuit. The POR circuit is used to receive an input voltage to generate a POR signal and generate a clock signal. The watchdog timer is used to generate a timeout signal according to the clock signal when the POR signal has an enabling voltage, the clock signal enabling generation of timeout pulses in the timeout signal at predetermined time intervals. The first AND gate including a first input terminal for receiving the POR signal; a second input terminal for receiving the timeout signal; and an output terminal for outputting a reset signal according to the POR signal and the timeout signal. The power management control circuit is used to reset an output current in response to a reset pulse in the reset signal.