Watchdog Timer Bus Traffic Reduction via CRC Verification
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Solution Overview
Problem
Conventional question and answer (Q&A) watchdog timers require large die size and multiple bus transfers, leading to increased bus traffic and limited system compatibility, which hampers system performance in environments with heavy communication demands.
Innovation Solution
A data processing system with a power management integrated circuit (PMIC) acting as a system watchdog timer, where the data processor calculates and verifies error codes, reducing the need for repeated bus transfers by using cyclic redundancy check (CRC) operations to maintain Q&A functionality while minimizing bus traffic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional Q&A watchdog timers use multiple bus transfers for question and answer verification, then the watchdog functionality and security are improved, but bus traffic increases and system performance deteriorates
Solution Approach 1:
The patent combines the question and answer verification process into a single bus transfer operation. The watchdog timer sends a question signal, the processor responds with an answer and error code, and the watchdog timer verifies the answer all within one bus cycle, eliminating the need for multiple separate bus transfers required by conventional Q&A watchdog timers.
Solution Approach 2:
The patent performs preliminary error code calculation and verification within the single bus transfer cycle. The processor pre-calculates the error code based on the question, and the watchdog timer pre-preares the verification logic, allowing the entire Q&A process to complete in one bus transfer without requiring subsequent verification transfers.
2Reliability
If conventional Q&A watchdog timers perform multiple bus transfers for error code verification, then the error detection capability is improved, but the die size and device complexity increase
Solution Approach 1:
The patent implements a universal error code verification mechanism that handles both question and answer verification within the same hardware structure. The watchdog timer uses the same bus interface and verification logic for both the question signal and the answer signal, eliminating the need for separate dedicated circuits for each function and reducing overall die size.
3Reliability
If conventional Q&A watchdog timers use custom algorithms and software for question and answer processing, then the watchdog security is improved, but system compatibility and ease of operation decrease
Solution Approach 1:
The patent implements self-service verification where the watchdog timer automatically generates questions, receives answers from the processor, and verifies the error codes without requiring external intervention or complex software algorithms. The hardware structure performs the verification function autonomously, improving system compatibility while maintaining security.
Data Source
AI summary
A method of performing a system watchdog operation of a data processing system using a system watchdog timer includes creating an initial question, starting a timer of the system watchdog timer, receiving an initial answer and an initial data code, calculating an expected data code in response to the initial question, and comparing the initial data code to the expected data code. In response to a mismatch between the initial data code and the expected data code, a bus error signal is generated. In response to a match, the initial answer is compared to the initial question, and in response to a match between the initial answer and the initial question, the timer is reset and the initial data code is stored as a subsequent question, but in response to a mismatch, a remedial action of the data processing system is performed.