Watchdog Timer With Dual Timeout Periods For Microcontroller Reset Control
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Solution Overview
Problem
Conventional watchdog timers have a fixed operation period and cannot be deactivated without compromising their integrity, leading to potential system resets during oscillator startup or graceful power down, which limits their reliability.
Innovation Solution
A watchdog timer unit is configured with two selectable time periods, allowing automatic switching from a first, potentially endless, time period to a second time period upon receipt of a clear watchdog signal, using flip-flops and timers to control reset outputs and clock signals, ensuring the timer is not activated during power-up or graceful power down.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the watchdog timer is deactivated by software according to conventional systems, then the watchdog timeout can be extended, but the integrity of the timer is compromised and reliability is reduced
Solution Approach 1:
The patent implements dynamic timeout periods by providing multiple predefined watchdog timeout values (first timeout period, second timeout period, third timeout period) that are automatically selected based on the operational state of the microcontroller. The system transitions between different timeout durations without requiring software intervention to modify the timer, thus maintaining integrity while adapting to different operational phases.
Solution Approach 2:
The patent changes the timeout parameter automatically based on operational conditions. During power-up and initialization, a first (longer) timeout period is applied. During normal operation, a second (shorter) timeout period is applied. This parameter change is controlled by hardware state detection rather than software commands, preserving timer integrity while extending timeout when needed.
2Reliability
If the watchdog timer is active during power-up and initialization, then system monitoring is maintained, but unintended system resets occur during oscillator startup and configuration code execution
Solution Approach 1:
The patent applies different timeout characteristics during different operational phases. During power-up and initialization, the first timeout period (which can be effectively endless or very long) prevents premature resets. During normal operation, the second timeout period provides active monitoring. This dynamic adaptation resolves the contradiction between maintaining monitoring and ensuring power-up stability.
Solution Approach 2:
The system prepares for potential timeouts during power-up by providing an extended first timeout period before normal operation begins. This preliminary action allows the microcontroller to complete critical initialization tasks (oscillator startup, configuration code execution) without the risk of unintended resets, while still having monitoring capability ready for normal operation.
3Device complexity
If the watchdog timer has a fixed operation period, then the timer structure is simple, but the timer cannot adapt to different operational phases such as power-up and normal operation
Solution Approach 1:
The patent implements a dynamic timeout system with multiple predefined periods (first, second, and third timeout periods) that are automatically selected based on operational state. The system transitions between these different timeout durations without requiring complex software control or modifying the basic timer structure, achieving adaptability while maintaining relatively simple hardware architecture.
Solution Approach 2:
The watchdog timer is designed to serve multiple functions across different operational phases. The same timer hardware provides both the extended timeout during power-up/initialization and the normal timeout during operation, simply by switching between different preset values. This multi-functionality eliminates the need for separate timer circuits for different phases.
Data Source
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AI summary
A microcontroller may comprise a central processing unit coupled with a plurality of peripheral devices through a system bus; and a watchdog timer unit receiving a clear watchdog signal and being configured to generate a watchdog timeout signal for resetting the microcontroller, wherein the watchdog timer unit is further configured to define a first and a second watchdog timeout period through a first and a second timer, respectively, further having logic to select the first or the second timer, wherein the clear watchdog signal resets the first and second timer.