Watchdog Timer Circuit Low Power Mode Deactivation
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Solution Overview
Problem
Watchdog timer circuits in microcomputers face issues with unintended deactivation during low power consumption modes, leading to reliability concerns and difficulty in recovering from such states, especially due to CPU runaway or noise-induced interruptions.
Innovation Solution
A watchdog timer circuit that serially loads and holds external data signals, inhibiting timer count operations when the data matches a predefined pattern and restarting when the pattern changes, ensuring that the circuit is not easily deactivated and can quickly recover to an operable state by requiring concordance of multiple bits for pattern matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the watchdog timer circuit operation is interrupted during low power consumption mode, then power consumption is reduced, but system reliability deteriorates due to potential accidental deactivation
Solution Approach 1:
The circuit performs preliminary actions by requiring multiple conditions to be met simultaneously before deactivation (pattern matching + low power mode detection) and by pre-preparing recovery mechanisms (automatic restart capability). This prevents accidental deactivation while enabling intentional power savings.
Solution Approach 2:
The circuit uses feedback by continuously monitoring both the power consumption mode status and the data pattern input, and automatically adjusting its operation state based on this feedback. The circuit can detect when it has been accidentally deactivated and automatically recover, creating a self-correcting system.
2Reliability
If the watchdog timer circuit requires multiple conditions for deactivation, then reliability improves by preventing accidental deactivation, but device complexity increases
Solution Approach 1:
The deactivation control function is segmented into independent components: a pattern matching unit that compares input data with predefined patterns, a power mode detection unit that monitors low power consumption state, and a control unit that combines both conditions. This modular segmentation achieves reliable multi-condition control while keeping each component simple and manageable.
Data Source
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AI summary
A watchdog timer circuit (40) for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit (30) responsive to receipt of a count clock signal for counting it up, and a timer control circuit (20) which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit (20) interrupts the clock signal counting operation of the timer circuit (30). During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit (20) allows the timer circuit (30) to restart the clock signal counting operation.