Mode-Dependent Watchdog Timer Timeout Adjustment
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Solution Overview
Problem
Watchdog timers in processing systems face challenges in accurately detecting software errors in modes with varying clock frequencies, such as low-power modes, where the reset signal is sent less frequently, potentially leading to false software error indications.
Innovation Solution
Implementing a mode-dependent timeout mechanism that adjusts the watchdog timer's timeout period based on the processing system's operational mode, allowing the timeout value to change without interrupting active operations, and incorporating protection logic to prevent unauthorized reconfiguration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the watchdog timer uses a fixed timeout value locked during operation, then security against software corruption is improved, but adaptability to different operational modes (e.g., low-power mode with reduced clock frequency) deteriorates
Solution Approach 1:
The patent implements a mode register that can be written to change the watchdog timeout value based on operational mode. This dynamic configuration allows the system to adapt the timeout period to different clock frequencies (e.g., full speed vs. quarter speed modes) while maintaining security through controlled access via the mode register write operation.
Solution Approach 2:
The patent changes the timeout parameter of the watchdog timer based on the operational mode of the microcontroller. When the clock frequency changes (e.g., entering low-power mode), the timeout value is adjusted proportionally to maintain accurate error detection. This is achieved through a mode register that stores the selected timeout value corresponding to the current operational mode.
2Adaptability or versatility
If the watchdog timer timeout value is increased to accommodate lower clock frequencies, then adaptability to low-power modes is improved, but measurement precision of software error detection deteriorates
Solution Approach 1:
Instead of using a single fixed timeout value, the patent implements multiple timeout values stored in a mode register, each corresponding to a specific operational mode and clock frequency. This allows the system to select the appropriate timeout value dynamically, maintaining precise error detection across all modes without requiring an excessively large timeout value that would compromise detection accuracy.
3Adaptability or versatility
If the watchdog timer allows reconfiguration during operation, then adaptability to different modes is improved, but reliability against software corruption deteriorates
Solution Approach 1:
The patent implements a mode register that can be written to during operation to change the watchdog timeout value. This dynamic reconfiguration capability allows adaptation to different operational modes while maintaining reliability through controlled access mechanisms that prevent unauthorized or erroneous modification of the timeout settings.
Data Source
AI summary
A method and apparatus to operate a watchdog timer having a first time out period in a processing system. The watchdog timer receives an indication of a change in a mode of operation in the processing system. In response to the change in the mode of operation of the processing system, the watchdog timer changes the time out period to a second time out period corresponding to the new mode of operation.