Window Watchdog Timer with Adjustable Timing and Oscillator Diagnosis

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Solution Overview

Problem

Existing window type watchdog timers have limited design flexibility and require external components to adjust determination times, and they cannot diagnose abnormalities in the oscillation circuit, which may lead to inappropriate monitoring of microcomputer operation.

Innovation Solution

A window type watchdog timer with an oscillation circuit generating a reference clock signal, a frequency dividing circuit, and a monitoring circuit that detects errors and abnormalities, allowing for variable setting of determination times and self-diagnosis capabilities using multiple frequency-divided clock signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If external components (resistor or capacitor) are used to adjust determination times in the watchdog timer, then the determination times can be changed, but the design flexibility is limited and external terminals are required

Engineering Contradiction:
Improvedetermination time adjustment flexibilityVSAvoidexternal component requirement
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the external component functionality into internal circuits. The determination time adjustment function that previously required external resistors or capacitors is now integrated into the watchdog timer circuit itself through internal resistance/capacitance elements and control circuits, eliminating external component requirements while maintaining adjustment capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The control circuit serves multiple functions: it controls the oscillation circuit frequency, adjusts determination times, and manages the frequency division ratio. This multi-functional design replaces what previously required separate external components, improving adaptability while reducing device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If the oscillation circuit frequency deviates due to aged deterioration or failure, then the watchdog timer cannot detect the abnormality, but continuing operation with abnormal monitoring is inappropriate

Engineering Contradiction:
Improveabnormality detection capabilityVSAvoidoscillation circuit abnormality detection
Core Design Contradiction:
ReliabilityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent implements feedback mechanisms where the control circuit continuously monitors the oscillation circuit output frequency and adjusts it accordingly. The control circuit receives feedback about frequency deviations and makes real-time corrections, enabling detection and compensation of aged deterioration or failure conditions

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The watchdog timer performs self-diagnosis through the control circuit monitoring its own oscillation circuit. The system uses its internal resources to detect and correct its own abnormalities without external intervention, improving reliability by enabling autonomous abnormality detection

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11429468B2Window type watchdog timer and semiconductor device
Publication Date: 2022.08.30 ROHM CO LTD
  • US11429468B2 patent drawing
  • US11429468B2 patent drawing
  • US11429468B2 patent drawing

AI summary

A window type watchdog timer includes a frequency dividing circuit for generating a frequency-divided clock signal by dividing a frequency of a reference clock signal; a monitoring circuit for monitoring occurrence of a first error in which clear control from a target device is interrupted for a first time or more, and occurrence of a second error in which an interval between two consecutive clear controls from the target device is shorter than a second time shorter than the first time, based on the frequency-divided clock signal; and outputting an error signal when the first error or the second error is detected; and a setting circuit for variably setting the first time and the second time by variably setting a frequency division ratio in the frequency dividing circuit and variably setting a detection condition of the first error and the second error.