Watchdog Timer Datalogging Circuit for OS Hang Failures

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Solution Overview

Problem

Existing data logging methods in computing devices fail to capture failure modes when the operating system is hung or unresponsive, preventing the collection of critical data for hardware and software improvements.

Innovation Solution

A watchdog timer triggers a system management circuit to access functional circuits via dedicated point-to-point interfaces, halting and logging information from these circuits to store in memory, even when the communication fabric is unresponsive.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If software-based data logging is used to collect data when unexpected behavior is detected, then data can be collected for analysis, but the system fails to log data when the operating system is hung or unresponsive

Engineering Contradiction:
Improvedata logging reliabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a system management circuit as an intermediary component that operates independently from the operating system to trigger data logging. This circuit monitors system health and activates logging mechanisms even when the OS is unresponsive, ensuring reliable data collection without requiring complex software coordination.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system management circuit performs self-service by autonomously detecting system failures and triggering data logging without external intervention. This autonomous operation ensures that critical failure data is captured even when the operating system cannot respond to logging requests.

Inventive Principle:
Principle #25Self-service

2Reliability

If dedicated point-to-point interfaces are used for system management circuit to access functional circuits, then data access is reliable during fabric failures, but the device complexity increases

Engineering Contradiction:
Improvedata access reliabilityVSAvoidinterface complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the communication path by implementing dedicated point-to-point interfaces between the system management circuit and functional circuits. This segmentation isolates critical management traffic from the general-purpose communication fabric, ensuring that management operations can proceed even when the fabric fails, despite increasing overall interface complexity.

Inventive Principle:
Principle #1Segmentation

3Measurement precision

If the system halts functional circuits to capture state information, then accurate failure state data is captured, but system productivity is reduced

Engineering Contradiction:
Improvefailure state capture accuracyVSAvoidsystem throughput
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The system performs preliminary actions by halting functional circuits and capturing their state information immediately upon detecting a failure condition. This immediate action preserves the exact failure state for accurate analysis, preventing further changes that would compromise diagnostic precision, though it temporarily reduces system productivity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12360836B2Datalogging circuit triggered by a watchdog timer
Publication Date: 2025.07.15 APPLE INC
  • US12360836B2 patent drawing
  • US12360836B2 patent drawing
  • US12360836B2 patent drawing

AI summary

An apparatus includes a memory circuit, and an integrated circuit formed on a single semiconductor substrate and coupled to the memory circuit. The integrated circuit includes a watchdog timer, a plurality of functional circuits coupled together via a communication fabric, and a system management circuit coupled to the watchdog timer and to a subset of the functional circuits via respective dedicated point-to-point interfaces. A given functional circuit may be configured to repeatedly reset the watchdog timer before the watchdog timer expires. The system management circuit may be configured, in response to an expiration of the watchdog timer, to access information in the subset of the functional circuits via the respective point-to-point interfaces. The system management circuit may be further configured to store the accessed information in the memory circuit.