Wave-Like Capacitor Sidewalls for High-Density Memory
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Solution Overview
Problem
Current capacitor structures for memory, such as DRAM, face challenges in maintaining sufficient capacitance as semiconductor technology advances to smaller node sizes, making it difficult to increase the plate area effectively.
Innovation Solution
The development of capacitor structures with wave-like sidewalls is introduced, achieved through a manufacturing method involving a substrate with cylindrical bottom electrode layers and a method of forming patterned photoresist layers and spacers to create etch masks, resulting in holes with wave-like sidewall cross-sections that increase the plate area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional cylinder-type or pillar-type capacitor structures are used, then the manufacturing process is relatively simple, but the plate area and capacitance are insufficient for advanced technology nodes
Solution Approach 1:
The patent applies curvature by forming wave-like cross-sections on the capacitor structures instead of conventional cylindrical or planar shapes. The wave-like pattern increases the surface area of the plates while maintaining a compact footprint, directly addressing the need for larger plate area without proportionally increasing the device footprint.
Solution Approach 2:
The invention transitions from two-dimensional planar or simple cylindrical plates to three-dimensional wave-like structures with varying cross-sections. This dimensional complexity allows the plates to occupy more space within the same lateral footprint, effectively increasing the plate area and capacitance for advanced technology nodes.
2Productivity
If the device size is reduced to achieve higher integration density, then the storage capacity increases, but the capacitance of each memory cell decreases
Solution Approach 1:
By implementing wave-like cross-sections on the capacitor structures, the patent increases the effective plate surface area within a reduced lateral footprint. This curvature-based approach allows smaller devices to maintain adequate capacitance values despite the reduced overall size, enabling higher integration density without sacrificing individual cell performance.
Solution Approach 2:
The wave-like structures effectively nest additional plate surface area within the compact capacitor structure. The multiple undulations of the wave pattern create nested regions that maximize the use of available space, allowing sufficient capacitance to be achieved within smaller device dimensions required for high-density integration.
Data Source
AI summary
A method of manufacturing a capacitor structure of memory, including forming a patterned photoresist layer on a hard mask layer and spacers on sidewalls of the patterned photoresist layer, perform a first etch process to remove uncovered hard mask layer so as to form first patterned hard mask layer and expose first portion of the dielectric layer, lowering a surface of the first portion of dielectric layer, perform a second etch process to remove uncovered first patterned hard mask layer so as to form second patterned hard mask layer and expose second portion of the dielectric layer, and performing a hole etching process to form first holes and second holes respectively in the first portion and the second portion of dielectric layer, wherein sidewalls of the first holes and second holes have wavelike cross-sections, and the wavelike cross-sections of first holes and second holes are shifted vertically by a distance.