Wave Pipeline Synchronous Stage Latency Reduction
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Solution Overview
Problem
Current wave pipelines in memory devices require multiple latch stages to align data and clock signals, leading to increased latency and power consumption due to the need for separate delay circuits for each stage.
Innovation Solution
Incorporating synchronous stages in the wave pipeline, where both data and clock signals are delayed equally, reducing the number of latch stages needed and eliminating the requirement for additional delay circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple latch stages are used to align data and clock signals in a wave pipeline, then signal alignment is achieved, but latency and power consumption increase
Solution Approach 1:
The patent extracts the delay function from separate delay circuits and integrates it directly into the latch stages. Each latch stage now inherently provides both data latching and clock delay functions, eliminating the need for additional standalone delay circuits and reducing overall pipeline latency while maintaining signal alignment.
Solution Approach 2:
The patent merges the delay circuit functionality with the latch stage functionality. Instead of having separate delay circuits for each latch stage, the delay function is integrated into the latch stage itself, combining two functions (latching and delaying) into a single unified stage, thereby reducing the number of components and latency.
2Reliability
If multiple latch stages with separate delay circuits are used, then data and clock signals are aligned, but device complexity increases
Solution Approach 1:
The patent merges the delay circuit functionality with the latch stage functionality. Instead of having separate delay circuits for each latch stage, the delay function is integrated into the latch stage itself, combining two functions (latching and delaying) into a single unified stage, thereby reducing the number of components and complexity.
Solution Approach 2:
The latch stages are designed to perform multiple functions: data latching, clock signal delay, and signal alignment all within the same stage. This multi-functionality reduces the overall number of components needed in the wave pipeline, simplifying the device architecture while maintaining signal integrity.
3Reliability
If multiple latch stages with separate delay circuits are used, then signal alignment is maintained, but power consumption increases
Solution Approach 1:
The patent merges the delay circuit functionality with the latch stage functionality. Instead of having separate delay circuits for each latch stage, the delay function is integrated into the latch stage itself, combining two functions (latching and delaying) into a single unified stage, thereby reducing the number of components and power consumption.
Solution Approach 2:
The patent extracts the delay function from separate delay circuits and integrates it directly into the latch stages. Each latch stage now inherently provides both data latching and clock delay functions, eliminating the need for additional standalone delay circuits and reducing overall power consumption.
Data Source
AI summary
A wave pipeline includes a data path and a clock path. The data path includes a plurality of wave pipeline data stages and a synchronous data stage. The synchronous data stage includes a first data latch to latch the data from the synchronous data stage. The synchronous data stage is between a first wave pipeline data stage of the plurality of wave pipeline data stages and a second wave pipeline data stage of the plurality of wave pipeline data stages. The clock path corresponds to the plurality of wave pipeline data stages. The first data latch latches the data from the synchronous data stage in response to a clock signal on the clock path.