Waveform Generation Circuit Using Sequenced Dead-Time Control
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Solution Overview
Problem
Conventional waveform generation circuits require large memory spaces to store data for both signal components and dead times in RF pulse train signals, such as radar signals, due to the need for storing waveform data for dead times, which is inefficient in terms of memory usage.
Innovation Solution
A waveform generation circuit with improved sequence control that stores only signal component data in waveform memory and uses sequence memory to control the generation of dead times through counters, eliminating the need for storing dead time data in waveform memory by using sequence control data to manage wait times, signal component lengths, and repeat counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If waveform data for both signal components and dead times are stored in waveform memory, then complete radar signal generation is achieved, but memory size requirements increase significantly
Solution Approach 1:
The patent segments the waveform data into two distinct parts: signal component data stored in waveform memory and dead time control data stored in sequence memory. This segmentation allows the waveform memory to store only the essential signal data while the sequence memory handles the dead time control, thereby reducing the memory size requirement for waveform memory while maintaining complete radar signal generation capability.
Solution Approach 2:
The sequence memory acts as an intermediary between the waveform memory and the counters. It stores sequence control data that includes addresses pointing to signal components in waveform memory and controls the wait counters to generate dead times. This intermediary structure enables the system to generate complete radar signals with both signal components and dead times without requiring waveform memory to store redundant dead time data.
2Quantity of substance
If waveform memory stores only signal component data, then memory usage is optimized, but dead time generation control becomes more complex
Solution Approach 1:
The sequence memory serves multiple functions: it stores addresses of signal components in waveform memory, generates control signals for wait counters to create dead times, and coordinates the operation of address counters and signal component length counters. This multi-functionality consolidates the control logic in a single component, reducing overall system complexity despite the optimized memory usage.
Solution Approach 2:
The system implements feedback mechanisms where the sequence control data in sequence memory provides addresses and control signals that are fed back to the waveform memory and counters. The wait counters use the sequence control data to generate dead times, and the address counters use the same data to retrieve signal components, creating a coordinated feedback loop that manages the complexity of dead time generation while maintaining efficient memory usage.
3Ease of operation
If dead time data is squeezed into signal components in waveform memory, then all data is stored in one location, but memory space is wasted during dead time periods
Solution Approach 1:
The patent introduces dynamic control through sequence memory that manages the timing and retrieval of data. Instead of static storage where dead time data is squeezed into waveform memory, the system dynamically controls the generation of dead times using wait counters and sequence control data. This dynamic approach allows the system to access only the necessary signal component data from waveform memory while generating dead times on-demand, thereby improving effective memory utilization without complicating data storage management.
Data Source
AI summary
A waveform generator has a waveform generation circuit storing waveform data for an analog waveform signals having dead time periods without the need for storing data on the dead time. A sequencer having a sequence memory stores sequence data that controls the sequencing of one or more signal components and associated dead times of the analog waveform signal. The timing of the dead time is controlled by a sampling clock and a wait time counter. The generation of the signal components is controlled by the sampling clock controlling the generation of addresses for a waveform memory storing digital data of the sampling components. The waveform memory digital data is converted to an analog waveform signal.