Waveform Detector Circuit for Sub-ps Phase Sensing in Synthesizers
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Solution Overview
Problem
Conventional frequency synthesizers face limitations in achieving low integrated jitter and phase noise due to limited bandwidth and scalability issues in phase-locked loop (PLL) circuits, and require high power consumption for precise phase detection, which restricts their ability to operate in fractional-N modes and handle process-voltage-temperature variations.
Innovation Solution
A waveform synthesizer employing oversampling and digital domain reconstruction to extract phase, amplitude, and harmonic information, using a wave-locked loop approach that samples the oscillator waveform multiple times per cycle, allowing for finer resolution and robustness against PVT variations, and enabling faster locking times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional time-to-digital converter (TDC) is used for phase detection, then phase detection capability is provided, but timing resolution is limited to one inverter delay (not much better than 7 ps for 28 nm CMOS technology)
Solution Approach 1:
The patent replaces the conventional mechanical/inverter-based TDC delay line with an analog-to-digital converter (ADC) based time-to-voltage conversion system. The time interval is converted to a voltage signal through integration, then digitized by an ADC, achieving sub-ps resolution without being constrained by inverter delay limitations.
2Measurement precision
If higher resolution TDC is achieved by spending more power, then timing resolution improves, but power consumption increases
Solution Approach 1:
The patent substitutes the high-power multi-stage inverter chain TDC with an ADC-based system that uses capacitive integration and analog-to-digital conversion. This approach achieves superior timing resolution with significantly reduced power consumption by avoiding the need for multiple high-speed inverter stages.
3Reliability
If conventional PLL with wide bandwidth is used to suppress phase noise, then integrated jitter performance improves, but achievable bandwidth is limited to less than 1/10 of the reference clock due to system stability
Solution Approach 1:
The patent replaces the conventional analog PLL with an all-digital PLL architecture that uses ADC-based time-to-voltage conversion and digital signal processing. This substitution enables achieving bandwidths greater than 1/10 of the reference clock while maintaining low phase noise, as the digital architecture allows for more flexible and precise control without the stability constraints of analog loop filters.
4Reliability
If analog loop filters are used in PLL, then phase noise suppression is achieved, but the filters are not scalable as technology advances
Solution Approach 1:
The patent substitutes analog loop filters with digital signal processing algorithms implemented in the digital domain. The phase error correction is achieved through digital filtering and processing of the ADC-generated digital signals, enabling scalability with technology advances and allowing for flexible adjustment of filtering characteristics without being constrained by analog component limitations.
5Measurement precision
If sub-sampling phase detector with ADC is used, then fine resolution is achieved, but the architecture is restricted to integer-N operation and suffers from nonlinear conversion
Solution Approach 1:
The patent implements a dynamic fractional-N operation mode that allows the reference frequency division ratio to be programmably adjusted. This enables the system to operate in both integer-N and fractional-N modes by dynamically changing the division ratio in the feedback path, overcoming the restriction of conventional sub-sampling phase detectors to integer-N operation only.
Solution Approach 2:
The patent changes the conversion characteristics by using a programmable reference frequency divider that can operate at multiple division ratios. This parameter adjustment enables linear conversion characteristics across both integer and fractional divisions, eliminating the nonlinear conversion limitation of fixed integer-N sub-sampling detectors.
Data Source
AI summary
A waveform synthesizer comprises a controllable oscillator for generating an oscillator waveform having an oscillator cycle; a reference input for accepting a reference signal having a reference cycle; and a waveform detector coupled to said oscillator and said reference input. The waveform detector is arranged to sample said waveform in response to said reference input and to determine waveform information about said oscillator. The waveform information is operative to adjust said controllable oscillator.