Waveform Reconstruction Emulation Logic Gate Analysis
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Solution Overview
Problem
Conventional emulation environments face inefficiencies in hardware and communication resources when dealing with highly complex integrated circuits, particularly in advanced processes like 22 nanometer and below, due to the need to transfer large amounts of data for billions of logic circuits and signals over multiple clock cycles, leading to significant strain on computing resources and prolonged testing times.
Innovation Solution
The system simulates logic circuits by constructing waveforms based on traced signals over a time frame including multiple clock cycles, rather than per clock cycle, selectively analyzing input signals only during durations where the output depends on the input, and omitting analysis during independent durations, thereby reducing the computational resources required and improving simulation speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional emulation transfers data for all billions of signals over multiple clock cycles, then complete emulation results are obtained, but computing resources are significantly strained and testing time is prolonged
Solution Approach 1:
The patent extracts only the essential traced signals from the complete emulation data set, separating critical timing and logic information from the overwhelming volume of unnecessary signal data. This extraction approach maintains emulation accuracy for verified functions while dramatically reducing data transfer requirements and testing time.
Solution Approach 2:
Instead of processing all billions of signals completely, the patent applies partial action by focusing computational resources only on traced signals that are critical for verification. This partial processing approach achieves sufficient emulation accuracy for design validation without the excessive computational burden of complete signal analysis.
2Reliability
If conventional emulation transfers data for all signals, then comprehensive verification is achieved, but hardware resources are significantly consumed
Solution Approach 1:
The patent extracts and processes only the traced signals that are essential for verification, removing unnecessary computational overhead from analyzing all billion-scale signals. This extraction maintains verification reliability for critical functions while reducing computing resource consumption and energy usage.
Solution Approach 2:
The patent applies partial action by performing complete verification analysis only on traced signals rather than all signals. This approach achieves sufficient verification reliability for design validation while avoiding excessive computing resource consumption and energy waste on redundant data processing.
3Measurement precision
If conventional emulation processes data per clock cycle, then detailed timing analysis is achieved, but simulation time increases significantly
Solution Approach 1:
The patent merges multiple clock cycle processing into a single consolidated processing step by capturing traced signal values across entire time frames. This merging maintains detailed timing analysis precision for verification while dramatically reducing simulation time by eliminating repetitive per-cycle processing overhead.
Solution Approach 2:
Instead of continuous per-clock-cycle processing, the patent implements periodic action by processing traced signals at strategic time points within time frames. This approach preserves essential timing analysis precision while reducing simulation time by avoiding unnecessary continuous processing during each clock cycle.
4Reliability
If conventional emulation traces all signals, then complete design verification is achieved, but communication bandwidth requirements increase
Solution Approach 1:
The patent extracts only the essential traced signals from the complete set of billion-scale design signals, separating critical verification data from redundant information. This extraction maintains verification completeness for traced functions while reducing communication bandwidth requirements and data transfer volume by orders of magnitude.
Data Source
AI summary
A disclosed system of an emulation environment performs a simulation to construct a waveform of a target signal based on signals traced by an emulator for a time frame including multiple clock cycles. In one embodiment, a simulation is performed in a manner that an input of the logic gate, in a first duration of the time frame at which an output of the logic gate depends on the input, is analyzed to obtain the output, and the input of the logic gate, in a second duration of the time frame at which the output of the logic gate is independent, is omitted. In one aspect, the input of the logic gate is simulated for the first duration based on a periodicity in a waveform of the input in the first duration.