Waveform Generator Using Clock Division for Low-Frequency DAC Output
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Solution Overview
Problem
High-speed test apparatuses struggle to effectively test semiconductor devices with low-speed analog circuits due to limitations in minimum sampling frequency and operation frequency, making it difficult to generate waveforms suitable for devices operating at lower frequencies.
Innovation Solution
A waveform generator is designed with a memory to retain pattern data, a clock signal generator, and a digital-to-analog converter (DAC) that allows for frequency division of the clock signal, enabling the DAC to output waveforms at a lower frequency than the clock signal, thereby extending the sampling period and allowing for testing of devices with lower operation frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed DAC is used to meet high-speed testing requirements, then the testing speed and performance are improved, but the minimum sampling frequency limits the ability to test low-speed semiconductor devices
Solution Approach 1:
The patent segments the relationship between clock signal frequency and waveform output frequency by introducing a frequency divider. The clock signal generator operates at high speed while the frequency divider segments the frequency conversion process, allowing the DAC to receive high-speed clock signals but output waveforms at lower frequencies matching the device under test. This resolves the contradiction by separating the high-speed operation requirement from the actual waveform frequency requirement.
Solution Approach 2:
The frequency divider acts as an intermediary component between the high-speed clock signal generator and the DAC. It mediates the frequency mismatch by converting the high-speed clock signal into a lower frequency signal that matches the device under test, enabling the high-speed DAC to test low-speed devices without being limited by its minimum sampling frequency.
2Adaptability or versatility
If the clock signal frequency is reduced to match low-speed devices, then low-speed device testing becomes possible, but the testing throughput and productivity decrease
Solution Approach 1:
The system segments the frequency conversion function into a dedicated frequency divider component. This allows the clock signal generator to maintain high frequency for productivity while the frequency divider segments the frequency adaptation process for low-speed device compatibility, resolving the contradiction between testing throughput and device compatibility.
Solution Approach 2:
The frequency divider enables dynamic frequency adjustment, allowing the system to adapt the waveform output frequency to match different device speeds while maintaining high-speed operation capability. This dynamic frequency conversion resolves the contradiction by making the system adaptable to both high-speed and low-speed devices without sacrificing productivity.
3Speed
If pattern data is repeated in memory to extend sampling period, then low-frequency waveform generation is achieved, but the memory usage efficiency decreases and complexity increases
Solution Approach 1:
The frequency divider serves as an intermediary that eliminates the need for complex memory data structures. Instead of repeating pattern data in memory, the frequency divider mediates between the high-speed clock and the DAC, providing the necessary frequency division while keeping the memory structure simple and efficient.
Solution Approach 2:
The patent replaces the mechanical approach of repeating data in memory with an electronic frequency division mechanism. This substitution eliminates the complexity of managing repeated data patterns in memory while achieving the same effect of extending the sampling period, thereby reducing memory usage inefficiency and structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the testing of semiconductor devices with lower operation frequencies by allowing the frequency of the output waveform to be decreased, effectively extending the sampling period of the DAC and reducing the need for repeated data values in the waveform memory, thus improving the testing capability of devices with low-speed analog circuits.
Implementation Method 1
a digital-to-analog converter operative to output, at the frequency of the clock signal, a waveform based on the read pattern data
Data Source
AI summary
The purpose is to provide a waveform generator that generates signals with a frequency lower than the minimum sampling frequency of the DAC.In the waveform generator 10, the clock generator 106 generates a clock signal 140. The frequency divider 112 divides the frequency of the clock signal 140 and generates the frequency-divided clock signal 144. The reader 118 provides an address signal at the period of frequency-divided clock signal 144 for the waveform memory 120 and reads the pattern data from the waveform memory 120 into the DAC 130. The DAC 130 converts the data provided from the waveform generator 120 at the period of clock signal 140 into an analog value and outputs a waveform of arbitrary shape.