Waveform Generator Memory Layout for Flexible Multi-Channel Driving
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Solution Overview
Problem
Existing waveform generators face limitations in flexibility, memory efficiency, and signal routing due to the arrangement of memory arrays, especially in applications requiring a large number of channels, leading to inefficiencies in area occupation and signal connection.
Innovation Solution
A waveform generator utilizing a two-dimensional shift register system with parallel-operated unidimensional shift registers, allowing for compressed waveform representation and efficient storage, eliminating the need for conventional random access memory and reducing signal routing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory arrays are used to store waveform parameters, then waveform flexibility and design freedom are improved, but area occupation increases and signal routing complexity increases
Solution Approach 1:
The patent merges the waveform storage function with the shift register structure used for timing control. Instead of separate memory arrays, the waveform parameters are integrated into the shift register cells, allowing simultaneous storage of timing and amplitude information in a compact unified structure.
Solution Approach 2:
The shift register is designed to serve multiple functions: it controls both the timing sequence and stores the waveform amplitude parameters. This multi-functional approach eliminates the need for dedicated memory arrays, reducing area occupation while maintaining waveform flexibility.
2Adaptability or versatility
If separate memory blocks are used for each channel, then channel independence is improved, but area occupation increases due to dedicated circuitry for each block
Solution Approach 1:
The patent merges the waveform storage and timing control functions into a single shift register structure that serves all channels. The shift register cells are configured to provide both timing sequences and amplitude values, eliminating redundant dedicated circuitry for each channel while maintaining independent waveform control.
Solution Approach 2:
The patent transitions from separate one-dimensional memory blocks for each channel to a two-dimensional shift register structure where rows represent time steps and columns represent channels. This dimensional reorganization allows shared resources to serve multiple channels efficiently.
3Quantity of substance
If conventional memory arrays are used, then waveform storage capacity is improved, but signal routing complexity and connection line length increase
Solution Approach 1:
The patent merges waveform parameter storage with the timing control shift register, eliminating separate memory arrays and their associated complex routing. The integrated structure provides both timing and amplitude information through the same shift register output, simplifying signal paths.
Solution Approach 2:
The patent extracts the waveform storage function from separate memory arrays and integrates it directly into the shift register structure. This extraction eliminates the need for complex interconnections between memory arrays and timing control circuits.
Data Source
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AI summary
A waveform generator includes: a system control unit (2) and a plurality of channels, (3.1, ..., 3.N) controlled by the system control unit (2) and configured to supply driving signals (V1, ..., VM) for driving an array of transducers (5.1, ..., 5.N). Each channel includes: a sequential access memory (10) having a plurality of rows, each containing instruction words (W) for generating a respective step of a respective one of a plurality of waveforms, and a memory output (10a) defined by an output row at a fixed location. The sequential access memory (10) contains blocks of instruction words (W), each defining a respective waveform. Each channel also includes an internal control unit (12), configured to sequentially move the content of the sequential access memory (10), based on the instruction word (W) currently at the memory output (10a), so that sequences of instruction words (W) are provided at the output row (10a). A starting instruction word (W) of each block of instruction words (W) defining the waveform contains an identification tag (WT) identifying the waveform. The internal control unit (12) receives a reference tag (TR) from the system control unit (2) and sequentially shifts the sequential access memory (10) until one of the starting instruction words (W) that contains an identification tag (WT) matching the received reference tag (TR) is moved to the memory output (10a).