Waveform Jitter Insertion Using Time-Varying Allpass Filtering
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Solution Overview
Problem
Existing test and measurement instruments face challenges in efficiently inserting jitter into high-speed analog waveforms without complex and costly calibration of digital-to-analog converters (DACs), particularly at sample rates exceeding 200 Giga-samples per second, where oversampling methods become impractical.
Innovation Solution
A test and measurement instrument that introduces jitter into a digital signal using a filter with time-varying coefficients, specifically an allpass filter, allowing for periodic long-term jitter modulation without adjusting the DAC sample rate or oversampling, utilizing a filter modulation controller to switch coefficients and control group delays for accurate jitter insertion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sample clock of the DAC is varied to insert jitter into the generated analog waveform, then jitter insertion is achieved, but the calibration complexity and cost increase significantly for interleaved DAC systems
Solution Approach 1:
The patent introduces a jitter buffer as an intermediary component between the data source and the interleaved DACs. This buffer stores data samples and applies variable delays to different channels based on calibration data, thereby inserting jitter without requiring complex calibration of the DAC clocks themselves. The jitter buffer acts as a mediator that decouples the jitter insertion function from the DAC calibration complexity.
Solution Approach 2:
The system performs preliminary calibration by measuring the relative timing offsets between interleaved DACs and storing this calibration data in the jitter buffer. This preliminary action allows the system to pre-compute and store the necessary delay adjustments, eliminating the need for complex real-time calibration during operation. The calibration is done once and reused, reducing overall calibration complexity.
2Speed
If the DAC sample rate is increased to over 200 GS/s for high-speed waveform generation, then the speed and accuracy of jitter insertion improve, but the complexity and cost of calibration for interleaved DACs multiply significantly
Solution Approach 1:
The jitter buffer serves as an intermediary that handles the complex timing adjustments at lower speeds, allowing the high-speed DACs to operate at their full 200+ GS/s capability without being burdened by calibration complexity. The buffer absorbs the timing variations and applies precise delays, enabling the DACs to focus solely on high-speed conversion.
Solution Approach 2:
The system creates a simplified model of the timing relationships through calibration data stored in the jitter buffer. Instead of directly managing complex high-speed calibration, the system copies the essential timing information into pre-computed delay values that can be applied straightforwardly, reducing the complexity of operating at ultra-high sample rates.
3Reliability
If oversampling is used to insert jitter by moving edges to new locations and resampling at the DAC sample rate, then jitter insertion is achieved, but the method becomes impractical at sample rates over 200 GS/s due to the speed requirements of the DSP circuitry
Solution Approach 1:
The patent replaces the mechanical/computational approach of oversampling and resampling with a simpler memory-based approach. Instead of using DSP circuitry to perform complex resampling operations at ultra-high speeds, the system uses a jitter buffer with pre-stored calibration data to apply variable delays directly, substituting computational mechanics with a more practical memory-access-based solution.
Solution Approach 2:
The system performs the complex edge-moving and resampling calculations in advance during the calibration phase, storing the results as delay values in the jitter buffer. This preliminary action eliminates the need for real-time oversampling and resampling during high-speed operation, making the system practical at sample rates over 200 GS/s where real-time DSP would be too slow.
Data Source
AI summary
A test and measurement instrument for generating an analog waveform, including an interpolator configured to receive a digital signal and output interpolated samples of the digital signal at a sample rate, a filter modulation controller configured to output first filter coefficients at a first time and second filter coefficients at a second time, a convolver configured to generate a convolved signal by convolving the interpolated samples of the digital signal and the first filter coefficients and convolving the interpolated samples of the digital signal and the second filter coefficients; and a digital-to-analog converter configured to convert the convolved signal to an analog signal based on a fixed, constant clock signal.