Waveform Memory D/A Converter for CPU-Independent High-Speed Output

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Solution Overview

Problem

Conventional D/A converters face a decrease in actual conversion speed due to the dependency on CPU processing for digital value input, making high-speed D/A conversion difficult.

Innovation Solution

A D/A converter with a wave-form data-array memory and output-format data memory, allowing for sequential output of digital values and direct conversion to analog values, independent of CPU intervention, enabling high-speed wave form output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If digital values are written from outside for every predetermined period, then the D/A converter can perform sequential conversion, but the actual D/A conversion speed decreases due to dependency on external writing speed

Engineering Contradiction:
ImproveD/A conversion speedVSAvoidactual conversion throughput
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-loading multiple digital values into the D/A converter's internal memory before they are needed for conversion. This allows the converter to operate at its maximum internal speed without waiting for external writing, as the data is already prepared and stored in advance within the device.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary buffer memory structure within the D/A converter that decouples the external data input rate from the internal conversion rate. This intermediary storage allows asynchronous operation where data can be written at one speed and converted at another speed, resolving the speed mismatch problem.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If an analog signal processor calculates digital values for each D/A conversion, then conversion can be performed, but the D/A conversion speed cannot be made sufficiently high

Engineering Contradiction:
ImproveD/A conversion throughputVSAvoidconversion speed
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

Instead of calculating digital values at the moment of conversion, the patent pre-calculates and stores multiple digital values in advance in the internal memory. This eliminates the calculation bottleneck during the conversion process itself, allowing the D/A converter to operate at its maximum speed without being limited by real-time calculation requirements.

Inventive Principle:
Principle #10Preliminary action

3Speed

If CPU intervention is used for digital value input, then control is maintained, but high-speed D/A conversion becomes difficult to achieve

Engineering Contradiction:
ImproveD/A conversion speedVSAvoidCPU dependency
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent enables the D/A converter to serve itself by incorporating internal memory and control logic that allows it to autonomously retrieve and convert pre-loaded digital values without requiring continuous CPU intervention. The device manages its own operation cycle, reading from its internal buffer and performing conversions independently, thereby achieving high speed while reducing CPU burden.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent segments the D/A converter functionality into distinct modules: an internal memory unit for storing digital values, a control unit for managing the conversion sequence, and the D/A conversion unit itself. This segmentation allows each component to operate independently and efficiently, with the control unit coordinating operations without requiring external CPU involvement for each conversion cycle.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8963756B2D/A converter, peripheral device, and PLC
Publication Date: 2015.02.24 MITSUBISHI ELECTRIC CORP
  • US8963756B2 patent drawing
  • US8963756B2 patent drawing
  • US8963756B2 patent drawing

AI summary

A D/A converter according to the present invention includes a wave-form data-array memory means for memorizing a wave-form data array configured of a plurality of digital values, a wave-form output-format data memory means for memorizing wave-form output-format data designating a wave-form output period, a digital value output means for sequentially reading out the digital values for each wave-form output period from the wave-form data-array memory means and outputting the values, and a D/A conversion means for converting the digital values outputted from the digital value output means into analog-data values.