Waveform Propagation Timing Model for Circuit Design
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Solution Overview
Problem
Current electronic design automation (EDA) methods face challenges in achieving accurate and fast delay calculations for circuit designs, leading to either inaccurate optimistic solutions or excessively pessimistic area overheads, and slow chip-level simulations that limit potential solutions.
Innovation Solution
The implementation of improved timing models with approximated waveform propagation, using a model that captures non-linear aspects of signal slew and delay, allowing for faster and more accurate calculations through a combination of single and double pole approximations, balancing accuracy and processing time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If chip-level simulation is used for accurate delay calculation, then measurement precision is improved, but productivity deteriorates due to very slow simulation speed
Solution Approach 1:
The patent segments the delay calculation process into two distinct levels: chip-level simulation for high accuracy on critical paths, and analytical modeling for fast estimation on non-critical paths. This segmentation allows the system to apply appropriate methods based on design stage and circuit criticality, resolving the contradiction between accuracy and speed by distributing computational effort selectively rather than uniformly across the entire design.
Solution Approach 2:
The patent changes the parameters of delay calculation by introducing stage-dependent modeling approaches. At early design stages, analytical models with adjustable parameters provide fast results for exploration. At later stages, chip-level simulation provides precise measurements. The system dynamically changes calculation parameters based on design progression, allowing both fast iteration during development and accurate verification at completion.
2Productivity
If analytical delay models are used for fast calculation, then productivity is improved, but measurement precision deteriorates due to inaccurate results
Solution Approach 1:
The patent introduces dynamics into the delay modeling by making the analytical model parameters adaptive rather than static. The model parameters are dynamically adjusted based on circuit characteristics and design stage, allowing the analytical model to maintain reasonable accuracy while preserving computational speed. This dynamic adaptation enables the model to capture non-linear effects without requiring full chip-level simulation.
Solution Approach 2:
The patent applies partial action by using analytical models for the majority of circuit elements where high precision is not critical, while reserving chip-level simulation for specific critical paths where accuracy is paramount. This selective application of modeling depth maintains overall productivity while ensuring accuracy where needed, avoiding the excessive computational cost of applying full simulation universally.
3Productivity
If optimistic delay estimates are used to reduce area overhead, then productivity is improved, but reliability deteriorates due to transition violations
Solution Approach 1:
The patent implements feedback mechanisms where delay calculation results from analytical models are continuously refined using data from chip-level simulation on critical paths. This feedback loop allows the system to learn from simulation results and improve analytical model accuracy over time. The feedback ensures that optimistic estimates do not compromise reliability, as the model parameters are adjusted based on actual simulation observations of timing violations and circuit behavior.
Data Source
AI summary
Electronic design automation systems, methods, and media are presented for a waveform propagation timing model for use with circuit designs and electronic design automation (EDA). One embodiment involves generating a gate output waveform for a circuit element using a driver input signal waveform and then generating a circuit element output waveform using the gate output waveform and an N-pole model of an interconnect with the first circuit element using moment matching. Timing values are then determined from the circuit element output waveform, such as delay and slew values. This waveform may then be propagated through the circuit, and an updated design generated using the timing values estimated from the modeled waveforms.