Phase-Interpolator Waveform Synthesis for Clock Mismatch Jitter
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Solution Overview
Problem
Conventional multiphase multiplexers suffer from deterministic jitter due to phase mismatch, which degrades timing margins at the receiver, primarily caused by device and capacitance mismatches in the layout, leading to suboptimal eye diagram performance.
Innovation Solution
An output waveform synthesizer utilizing 2N phase interpolators to control phase clock signals, grouped into N sets, with an eye opening monitoring unit and microcontroller to adjust clock overlap periods and phase alignments, ensuring independent control of rising and falling edges, and correcting duty cycle distortions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional multiphase multiplexer is used, then device structure is simple, but deterministic jitter increases due to phase mismatch
Solution Approach 1:
The phase control function is segmented into multiple independent phase interpolators (2N interpolators for N clock phases), where each interpolator independently controls the phase of a specific clock edge. This segmentation allows precise phase adjustment for each clock phase without affecting others, thereby reducing deterministic jitter while maintaining manageable device complexity through modular architecture.
Solution Approach 2:
The invention changes the control parameter from direct clock phase generation to phase interpolation with independent rise/fall delay control. By adjusting the interpolation ratio and delay parameters of each phase interpolator, the system achieves precise phase alignment and duty cycle correction, resolving the phase mismatch problem without requiring complex restructuring of the multiplexer.
2Reliability
If phase interpolators are used to control clock phases, then deterministic jitter is reduced, but device complexity increases
Solution Approach 1:
The phase interpolators serve multiple functions simultaneously: they generate multiphase clock signals, adjust phase alignment, control duty cycle, and reduce deterministic jitter. By making these components multi-functional, the invention reduces the need for separate dedicated circuits for each function, thereby managing device complexity while achieving superior timing performance.
Solution Approach 2:
The system includes an on-chip eye opening monitoring circuit that automatically measures the output eye diagram and feeds back to the microcontroller for real-time phase calibration. This self-service mechanism allows the system to automatically optimize its own performance without external intervention, reducing the need for complex external testing and calibration equipment.
3Manufacturing precision
If independent rise and fall delay control is implemented, then waveform precision is improved, but manufacturing complexity increases
Solution Approach 1:
The delay control is segmented into independent rise delay and fall delay paths for each clock phase, allowing separate optimization and tuning of each delay component. This segmentation enables standardization of delay cells and makes the layout more systematic and manufacturable, as each delay path can be implemented using identical modular delay elements.
Solution Approach 2:
The invention uses digitally controllable delay elements with adjustable delay parameters, allowing precise delay adjustment through digital control codes rather than requiring precise analog component matching. This parameter-based control approach simplifies manufacturing by reducing sensitivity to process variations and making the system more robust to layout variations.
4Measurement precision
If on-chip eye opening monitoring is added, then calibration precision is improved, but device complexity increases
Solution Approach 1:
The eye opening monitoring circuit serves as an intermediary between the output driver and the microcontroller, providing quantitative feedback about the output eye diagram quality. This intermediary measurement capability enables automated calibration algorithms to optimize phase alignment and duty cycle without requiring complex external measurement equipment, achieving high measurement precision through integrated on-chip monitoring.
Data Source
AI summary
Exemplary embodiments of the present invention relate to an output waveform synthesizer using phase interpolators and an on-chip eye opening monitoring (EOM) circuit for a low-power transmitter. In order to achieve both small area and low-power consumption in the transmitter design, a single-stage multiphase multiplexer operating in subrate is employed. The multiphase multiplexer is composed of parallelized open-drain NAND gates. In subrate transmitter architecture, the phase mismatch among multiphase clock signals degrades jitter performance significantly and is a critical bottleneck for its widespread use despite low power consumption. In order to overcome such mismatch problem, an area-and-power-efficient phase interpolator based waveform synthesizing scheme is developed.