Waveform Generator Trigger Alignment Without External DACs
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Solution Overview
Problem
Conventional waveform generators face challenges in aligning analog output signals with both periodic and non-periodic reference signals from target devices, often resulting in out-of-phase signals and requiring external DACs or PLLs, which increase costs and area overhead.
Innovation Solution
A waveform generator design incorporating a look-up table, digital-to-analog converter, rising-edge detector, LUT address capture module, digital comparator, and compensator module, allowing the generator to detect and align with input trigger signals, eliminating the need for external DACs and addressing PLL limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a pulse width modulator (PWM) block is used to adjust duty cycle and align the analog output signal with the reference signal, then phase alignment is improved, but area overhead and cost of production increase due to requiring an external DAC
Solution Approach 1:
The patent combines the DAC functionality with the waveform generator core, eliminating the need for an external DAC component. The LUT is enhanced with capture and compensator modules that work together with the integrated DAC to achieve phase alignment, thereby reducing area overhead while maintaining manufacturing precision.
Solution Approach 2:
The LUT is designed to serve multiple functions: storing waveform data, capturing trigger-aligned address values, and generating control signals for the DAC. This multi-functionality eliminates the need for separate external components, reducing overall device complexity while maintaining phase alignment capability.
2Manufacturing precision
If a phase-locked-loop (PLL) is used to generate a periodic output signal with phase relationship to the reference signal, then phase alignment is improved, but the system fails when the reference signal is non-periodic
Solution Approach 1:
The system dynamically adapts to both periodic and non-periodic reference signals by capturing the trigger signal's rising edge and using it to reload the LUT address. This dynamic address capture and reload mechanism allows the waveform generator to synchronize with any reference signal type, eliminating the PLL's limitation to periodic signals only.
Solution Approach 2:
The compensator module monitors the captured address value and generates a reload signal when alignment is achieved, creating a feedback loop that continuously maintains phase synchronization. This feedback mechanism works with both periodic and non-periodic triggers, providing universal adaptability.
3Device complexity
If the waveform generator uses a free-flowing analog output signal without prediction mechanism, then simplicity is maintained, but the output signal becomes out of phase with the reference signal
Solution Approach 1:
The system performs preliminary action by capturing the trigger signal's rising edge and pre-loading the corresponding LUT address value before the actual waveform generation. This advance preparation ensures that when the waveform is generated, it is already aligned with the reference signal, achieving phase accuracy without complex prediction mechanisms.
Solution Approach 2:
The waveform generator uses its own internal LUT and address capture mechanism to automatically align its output with the external trigger signal. The compensator module self-regulates by monitoring alignment and triggering LUT reloads as needed, maintaining phase accuracy through self-service rather than external intervention.
Data Source
AI summary
A waveform generator for providing an analog output signal to a target device includes a look-up-table (LUT) that stores a plurality of binary address values and a digital-to-analog converter (DAC) that generates the analog output signal. The waveform generator receives an input trigger signal from the target device when the target device is ready to receive the analog output signal. The waveform generator generates a synchronized input trigger signal and aligns the analog output signal with the synchronized input trigger signal by reloading the LUT with a binary address value of zero.