Wavefront Parallel Processor Reconfiguration for 5G Signal Flow
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Solution Overview
Problem
Existing processor architectures for signal processing in 5G and 6G wireless communications face challenges in flexibility, power consumption, and area efficiency, as they are either inflexible and costly (custom ASICs) or inefficient and costly (FPGAs) or lack adaptability (systolic arrays).
Innovation Solution
A configurable wavefront parallel processor (cWAFER) with individually programmable processing elements, a memory-less interconnection fabric, and a long configuration register that allows flexible data flow and configuration, enabling high throughput and energy efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If custom ASIC is used for signal processing, then processing performance is improved, but flexibility and area cost worsen
Solution Approach 1:
The processing element is designed as a universal unit that can perform multiple signal processing functions (FIR filtering, correlation, convolution, covariance operations) through reconfiguration of the same hardware resources. The configuration register allows the same PE to be adapted for different algorithms and data flow patterns, eliminating the need for custom ASICs for each application while maintaining high processing performance.
Solution Approach 2:
The architecture introduces dynamic reconfigurability through configuration registers that can change the behavior of processing elements during operation. The data flow direction, filter coefficients, and operational modes can be dynamically adjusted without hardware changes, providing flexibility comparable to software reconfiguration while maintaining ASIC-level performance.
2Adaptability or versatility
If FPGA is used for signal processing, then flexibility is improved, but power consumption and area efficiency worsen
Solution Approach 1:
The architecture segments the processing function into discrete, efficiently implemented building blocks (processing elements with specific functions like FIR filtering, correlation, convolution). Each segment is optimized for its specific operation but can be reconfigured through the configuration register, achieving FPGA-like flexibility with ASIC-level power efficiency by avoiding the overhead of fully programmable logic.
3Area of stationary object
If systolic array is used for signal processing, then area efficiency is improved, but adaptability worsens
Solution Approach 1:
Each processing element in the array is designed with specialized local functionality (e.g., specific filtering or correlation capabilities) that is optimized for area efficiency. The configuration register provides local reconfigurability, allowing each PE to be adapted to different operations without requiring the entire array to be reconfigured, thus maintaining high area efficiency while providing necessary adaptability.
4Adaptability or versatility
If reconfiguration is performed during operation, then adaptability is improved, but processing speed worsens
Solution Approach 1:
The configuration register is designed to accept reconfiguration commands that are processed in advance or during idle cycles, allowing the processing elements to be reconfigured without stalling the data flow. The architecture separates configuration control from data processing paths, enabling adaptability changes to be prepared and applied without disrupting the high-speed processing of active data streams.
Data Source
AI summary
An apparatus comprising: at least one processing element configured to process a data flow in at least one direction of a plurality of directions; a configuration register comprising at least one setting that determines the processing of the data flow with the at least one processing element; and a shift register configured to select data of the at least one processing element from the at least one direction, and to provide at least one shifted data sample to a plurality of slices configured to perform at least one arithmetic operation with the data flow; wherein at least one slice of the plurality of slices is configured with the at least one setting of the configuration register.