Waveguide-Active Component Integration With Trench-Filled SiN
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing silicon nitride waveguide manufacturing methods face challenges in integrating low-loss and anomalous-dispersion waveguides with semiconductor active components due to rough side walls and high aspect ratios, limiting their application in photonic integrated circuits.
Innovation Solution
An integrated structure and manufacturing method that includes a dielectric layer, waveguide structure, transition structure, active component structure, cover layer, via holes, and contact pads, where the waveguide structure is disposed on the dielectric layer, connected through a transition structure to the active component, and covered by a cover layer, with via holes and contact pads for improved light coupling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick silicon nitride is deposited first and etching is used to form waveguide structure, then low-loss and anomalous-dispersion waveguide can be achieved, but integration with semiconductor active components becomes difficult due to rough side walls
Solution Approach 1:
The patent segments the waveguide formation process into distinct steps: first forming trenches in the semiconductor layer, then filling with silicon nitride, and finally planarizing. This segmentation allows separate optimization of waveguide quality and integration compatibility, resolving the contradiction between low optical loss and ease of integration.
Solution Approach 2:
The patent performs preliminary trench formation and silicon nitride filling before final waveguide definition. By pre-defining the waveguide positions through trench etching and filling, the subsequent planarization and active component integration become easier while maintaining smooth waveguide sidewalls for low optical loss.
2Reliability
If thermal reflow is used to smoothen sidewall roughness, then optical loss is reduced, but monolithic integration with photodetectors remains difficult due to high aspect ratio
Solution Approach 1:
The patent adds a planarization dimension to the waveguide formation process. By introducing CMP planarization after trench filling, the high aspect ratio structure is transformed into a low aspect ratio structure with smooth top surface, enabling both low optical loss and easy integration without requiring thermal reflow.
Solution Approach 2:
The patent changes the surface morphology parameter through CMP planarization, transforming rough high aspect ratio sidewalls into smooth low aspect ratio surfaces. This parameter change achieves both low optical loss and compatibility with photodetector integration processes.
3Productivity
If direct etching of thick silicon nitride is used, then waveguide structure is formed quickly, but rough side walls cause large optical loss
Solution Approach 1:
The patent segments the waveguide formation into trench etching, silicon nitride filling, and CMP planarization steps. This segmentation replaces direct thick silicon nitride etching with a process that inherently produces smooth sidewalls, achieving both high productivity and low optical loss.
Solution Approach 2:
The patent introduces CMP planarization as an intermediary process between silicon nitride deposition and waveguide finalization. This intermediary step smooths the sidewalls without requiring re-etching, maintaining manufacturing speed while reducing optical loss from rough surfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high light coupling efficiency between silicon nitride waveguides and semiconductor active components, facilitating the production of low-loss photonic integrated circuits and nonlinear optical resonance cavities, compatible with CMOS processes for mass production.
Implementation Method 1
an ion implanting step, which includes performing an ion implantation process on the semiconductor layer to form a first doped portion and a second doped portion in the active component region
Implementation Method 2
a deposition layer polishing step, which includes performing a chemical-mechanical polishing process on the deposition layer to expose a surface in the semiconductor layer and the waveguide material filled in the waveguide trenches
Data Source
AI summary
A manufacturing method for an integrated structure of a waveguide and an active component is proposed. The manufacturing method includes providing a substrate including a dielectric layer and a semiconductor layer, and the semiconductor layer includes a waveguide region, a transition region and an active component region; etching the semiconductor layer to form a plurality of waveguide trenches; depositing a waveguide material on the semiconductor layer to form a deposition layer, and the waveguide trenches are filled with the waveguide material; performing an ion implantation process on the semiconductor layer to form a first doped portion and a second doped portion; etching the waveguide region, the transition region and the active component region to form a waveguide structure, a transition structure and an active component structure; depositing a cover layer on the dielectric layer; forming two via holes and two contact pads in the cover layer.