Semiconductor Optical Waveguide Mesa Width Control

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Solution Overview

Problem

Existing semiconductor optical waveguide devices face challenges in achieving stable optical transitions and controlling the transverse mode of light propagation due to variations in mesa widths, leading to high contact resistance and parasitic capacitance, which affect driving voltage and high-frequency characteristics.

Innovation Solution

A method for manufacturing semiconductor optical waveguide devices involves forming stacked semiconductor layers with vertically arranged core layers and cladding layers, using multiple etching masks to create mesas with specific width variations, and embedding dummy buried regions to control the waveguide structure and improve patterning precision, allowing for stable optical transitions and reduced parasitic capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the upper semiconductor mesa has a small width, then the optical coupling is improved, but the contact resistance increases

Engineering Contradiction:
Improveoptical coupling stabilityVSAvoidcontact resistance
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by creating different mesa widths at different locations along the waveguide structure. The upper mesa has a first width optimized for optical coupling, while the lower mesa has a second width optimized for electrical contact. This spatial variation in geometric properties allows each region to fulfill its specific function optimally without compromise.

Inventive Principle:
Principle #3Local quality

2Object-affected harmful factors

If the intermediate semiconductor mesa has a large width, then the electrical contact is improved, but the parasitic capacitance increases

Engineering Contradiction:
Improvecontact resistanceVSAvoidparasitic capacitance
Core Design Contradiction:
Object-affected harmful factorsVSObject-generated harmful factors

Solution Approach 1:

The patent implements local quality by varying the mesa width along the propagation direction. The intermediate mesa has a larger width specifically at the contact region to reduce contact resistance, while maintaining a smaller width in the optical waveguide region to minimize parasitic capacitance. This localized geometric optimization resolves the contradiction between electrical and optical performance.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If multiple etching masks are used to control mesa widths, then the manufacturing precision is improved, but the device complexity increases

Engineering Contradiction:
Improvemesa width controlVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the waveguide structure into distinct sections (upper mesa, intermediate mesa, lower mesa) with different width characteristics. Each section is formed through controlled etching processes using masks with specific patterns. This segmentation allows precise control of each mesa's dimensions while maintaining overall structural integrity and functionality.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9261649B2Method for manufacturing semiconductor optical waveguide device, and semiconductor optical waveguide device
Publication Date: 2016.02.16 SUMITOMO ELECTRIC INDUSTRIES LTD
  • US9261649B2 patent drawing
  • US9261649B2 patent drawing
  • US9261649B2 patent drawing

AI summary

A method for manufacturing a semiconductor optical waveguide device includes the steps of forming a waveguide mesa having first and second portions by etching a stacked semiconductor layer through a first mask; forming a dummy buried region embedding a top surface and side surfaces of the waveguide mesa; forming a second mask on the dummy buried region, the second mask having an opening on the first portion and having a pattern on the second portion; forming a third mask having an opening that reaches a top surface of the first portion, the third mask including a dummy buried mask formed by etching the dummy buried region through the second mask; forming an upper mesa by etching the waveguide mesa through the third mask; and after removing the third mask, forming a lower mesa by etching the stacked semiconductor layer, the lower mesa having a greater width than that of the upper mesa.