Waveguide Semiconductor Package for High-Speed Chip Integration
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Solution Overview
Problem
The complexity of manufacturing miniaturized semiconductor devices leads to issues such as poor structural configuration and delamination, resulting in yield loss and increased costs, due to the challenges in integrating multiple chips with high communication speed requirements.
Innovation Solution
A semiconductor structure and method involving a substrate with an interconnect structure, dielectric layer, conductive members, and a waveguide that converts electrical signals to electromagnetic signals for high-speed transmission, achieving data transfer rates greater than 10 gigabits per second with minimized energy loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple chips are integrated into a single semiconductor device using CoWoS operation, then functionality and communication speed are improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: forming through-substrate vias in the substrate, assembling chips on the substrate, and then forming interconnect structures. This segmentation allows each stage to be optimized independently, reducing overall manufacturing complexity while maintaining high communication speed through proper via and interconnect design
Solution Approach 2:
The patent utilizes three-dimensional integration by forming through-substrate vias that extend vertically through the substrate, enabling chips to be connected in multiple layers. This dimensional approach allows high-speed communication between stacked chips while managing manufacturing complexity through standardized via formation processes
2Volume of moving object
If miniaturization of semiconductor device is implemented, then device size is reduced, but structural configuration quality deteriorates
Solution Approach 1:
The patent applies different material properties and structural configurations to different regions: the substrate provides mechanical support with larger feature sizes, while the through-substrate vias and interconnect structures use specialized conductive materials optimized for electrical performance. This local quality approach maintains structural integrity despite miniaturization
Solution Approach 2:
The patent employs composite structures combining the substrate material with conductive materials filled in through-substrate vias, and additional dielectric and conductive layers in interconnect structures. These composite materials provide both mechanical strength and electrical performance required for miniaturized high-speed devices
3Adaptability or versatility
If more manufacturing operations are implemented in miniaturized scale, then functionality is enhanced, but yield loss increases
Solution Approach 1:
The patent performs preliminary actions by forming through-substrate vias in the substrate before chip assembly, and preparing the substrate surface with appropriate coatings and structures. These preliminary steps ensure that subsequent chip assembly and interconnect formation proceed smoothly, reducing defects and improving yield while enabling enhanced functionality
Solution Approach 2:
The patent incorporates protective measures by forming robust through-substrate vias that provide mechanical and electrical stability throughout subsequent manufacturing operations. The substrate structure is designed to cushion and absorb stresses from multiple processing steps, preventing delamination and structural failures that would reduce yield
4Quantity of substance
If chip integration density is increased, then device functionality is improved, but delamination of components occurs
Solution Approach 1:
The patent merges the substrate, through-substrate vias, chips, and interconnect structures into an integrated assembly where each component reinforces the others. The through-substrate vias act as anchors that mechanically bond chips to the substrate, preventing delamination even as integration density increases and thermal and mechanical stresses increase
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables ultra-high speed signal transmission exceeding 100 gigabits per second and high frequency operations, improving the performance and yield of semiconductor devices by addressing the structural and integration challenges in miniaturized manufacturing.
Implementation Method 1
a waveguide that converts electrical signals to electromagnetic signals for high-speed transmission
Data Source
AI summary
A method of manufacturing the semiconductor structure includes: providing a substrate; forming a first conductive via and a second conductive via extending in the substrate; depositing a first dielectric layer over the substrate and the first and second conductive vias; receiving a waveguide; moving the waveguide to a location over the first dielectric layer and aligning the waveguide with a position of the first dielectric layer; attaching the waveguide to the position of the first dielectric layer; forming a first conductive member and a second conductive member over the waveguide, the first conductive member and the second conductive member being in contact with the waveguide; and etching a backside of the substrate to electrically expose the first and second conductive vias. The first conductive member or the second conductive member is electrically connected to the first or second conductive via.