Optical Waveguide Integration Between Metal Routing Layers
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Solution Overview
Problem
In photonic integrated circuits, the incorporation of metal layers poses challenges such as excess loss and surface roughness in waveguides, particularly when routing optical signals between metal layers, limiting the proximity and real estate available for circuitry.
Innovation Solution
A process that enables independent waveguide layers to be routed between closely spaced metal layers, using intermetal dielectric levels with specific thicknesses and materials like silicon oxide, silicon nitride, and alumina, and incorporating metal vias and baffles for optical shielding to reduce waveguide cross-talk and stray light.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal layers are incorporated into photonic integrated circuits, then electrical connectivity and grounding are provided, but optical loss increases and surface roughness is introduced in waveguides
Solution Approach 1:
The patent segments the circuit into distinct photonic and electronic layers. Waveguide layers are separated from metal routing layers by intermetal dielectric layers, allowing optical and electrical functions to coexist without direct interaction. This segmentation enables independent optimization of each layer for its specific function.
Solution Approach 2:
Intermetal dielectric layers serve as intermediary materials between waveguide layers and metal routing layers. These dielectric layers act as optical isolators that prevent harmful metal-optical mode interactions while allowing electrical connectivity to be maintained through controlled vias and routing paths.
2Area of stationary object
If metal layers are placed close to waveguides, then real estate is saved and device compactness is improved, but optical loss and surface roughness increase
Solution Approach 1:
The patent utilizes vertical stacking of multiple waveguide layers and metal routing layers in the z-dimension. This allows compact 3D integration where waveguide layers can be positioned at different heights, enabling close proximity for area efficiency while maintaining adequate separation distances to minimize optical loss through the intermetal dielectric medium.
Solution Approach 2:
The patent optimizes the thickness and material composition of intermetal dielectric layers to achieve the right balance between compactness and optical performance. By controlling dielectric layer thickness parameters and selecting appropriate materials, the design achieves minimal optical loss while maximizing device compactness.
3Adaptability or versatility
If multiple optical routing layers are added between metal layers, then optical routing capability is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The intermetal dielectric layers serve multiple functions simultaneously: they provide electrical isolation between metal routing layers, act as optical cladding for waveguides, and serve as a medium for embedding waveguide structures. This multi-functionality reduces the need for additional dedicated layers, simplifying the overall device structure despite enhanced routing capabilities.
4Reliability
If vertical metal via height increases, then electrical connectivity between layers is improved, but lateral via extent must increase limiting available real estate
Solution Approach 1:
The patent employs nested via structures where smaller diameter via sections are positioned within larger diameter via sections at different heights. This nesting allows continuous electrical connectivity through tall vias while minimizing the lateral footprint at any given cross-section, preserving real estate for other circuit elements.
Data Source
AI summary
A photonic integrated circuit and a method for its manufacture are provided. In an embodiment, an intermetal dielectric layer, for example, a silicon oxide layer, is contiguous between an upper metal layer and a lower metal layer on a substrate. One or more waveguides having top and bottom faces are formed in respective waveguide layers within the intermetal dielectric layer between the upper and lower metal layers. There is a distance of at least 600 nm from the upper metal layer to the top face of the uppermost of the several waveguides. There is a distance of at least 600 nm from the lower metal layer to the bottom face of the lowermost of the several waveguides. The waveguides are formed of silicon nitride for longer wavelengths and alumina for shorter wavelengths. These dimensions and materials are favorable for CMOS processing, among other things.