Wavelet Compression Using Tiled SIMD Dot Products for Faster HPC I/O
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing data compression methods for High Performance Computer systems are not sufficiently fast for processing large volumes of data, leading to increased computing costs and making the use of compressed data during I/O processing unattractive.
Innovation Solution
A method of input data compression using a core with a central memory and operating cache memory, employing vector registers and cache lines to perform a two-dimensional wavelet transform with low and high band-pass filters, utilizing fused multiply-add instructions to accelerate dot product computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing data compression methods are used, then data compression is achieved, but processing speed is too slow for large volumes of data
Solution Approach 1:
The patent divides the input data array into multiple tiles, where each tile is further divided into data block columns. This segmentation allows parallel processing of different tiles by multiple cores and enables efficient cache utilization within each tile, significantly improving compression speed for large datasets
Solution Approach 2:
The patent replaces traditional scalar wavelet transform computations with vectorized operations using SIMD (Single Instruction, Multiple Data) instructions. By substituting sequential scalar mechanics with parallel vector mechanics, the processing throughput is dramatically increased while maintaining compression quality
2Quantity of substance
If wavelet transform is applied to compress large volumes of data, then compression ratio improves, but computing cost becomes too expensive
Solution Approach 1:
The patent performs preliminary organization of data into tiles with specific dimensional constraints before the wavelet transform. By pre-structuring the data to align with cache line boundaries and vector register widths, the subsequent compression operations can proceed efficiently without excessive computational overhead
Solution Approach 2:
The patent changes the processing parameters by using data block column dimensions that are multiples of cache line length and vector register length. This parameter adjustment enables optimal utilization of hardware resources, reducing computing cost while maintaining the ability to process large data volumes
3Speed
If traditional I/O processing is used, then simplicity is maintained, but processing speed is too slow compared to computing power
Solution Approach 1:
The patent substitutes traditional scalar-based I/O processing with vectorized wavelet transform operations that leverage SIMD instructions. This mechanical substitution enables the I/O processing speed to keep pace with the rapidly increasing computing power of modern HPC systems
Solution Approach 2:
The patent implements periodic processing by dividing data into tiles that can be processed in regular intervals by multiple cores. This periodic action structure allows the I/O processing to be systematically accelerated through parallel execution, matching the growth of computing power
Data Source
AI summary
A method of data compression performed by at least one core communicating with a central memory. The input data presents a two-dimensional input array formed by a plurality data items stored contiguously in the central memory according to a contiguous direction. The method comprises a step of wavelet transform comprising the following sub-steps: forming from the input array at least one tile comprising a plurality of consecutive data block columns, each data block column being formed by a plurality of lines of consecutive data items according to the contiguous direction, the length of each line being a multiple of the cache line length; and for each data block column computing dot products between a filter vector and each group of N lines using fused multiply-add instructions for the core.