Embedded Source/Drain Stressor Epitaxy for FinFET Contact Area
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Solution Overview
Problem
In the formation of Fin Field-Effect Transistors (FinFETs), the existing methods for creating source/drain regions result in merged epitaxy regions with planar top surfaces, leading to reduced contact area and increased contact resistance between the source/drain contact plugs and the underlying regions.
Innovation Solution
The introduction of an embedded stressor in the source/drain region with a wavy top surface, achieved through a multi-step epitaxy process, increases the contact area and reduces contact resistance by incorporating a higher dopant concentration and stressor layer that enhances dopant activation and stress distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxy regions are grown from recesses of neighboring semiconductor fins, then the source/drain regions are formed, but the epitaxy regions merge and form planar top surfaces that reduce contact area and increase contact resistance
Solution Approach 1:
The patent introduces a wavy top surface structure in the source/drain region through controlled epitaxial growth. This wavy surface, rather than being planar, increases the effective contact area between the source/drain contact plug and the underlying region. The curvature and undulations in the surface topology provide more interface area for electrical contact, thereby reducing contact resistance while maintaining the same footprint dimensions.
Solution Approach 2:
The patent applies different dopant concentrations at different locations within the source/drain region. By incorporating a stressor layer with higher dopant concentration in specific areas (particularly near the top surface where contact is made), the local electrical properties are enhanced. This local quality variation improves dopant activation and reduces contact resistance at the critical contact interface without requiring uniform high doping throughout the entire region.
2Reliability
If a multi-step epitaxy process with stressor layer is used, then dopant activation and contact area are improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent combines multiple functions into a single integrated structure. The stressor layer is formed as part of the epitaxial growth process itself, rather than as a separate post-processing step. This layer simultaneously provides mechanical stress to enhance dopant activation, serves as a dopant source, and creates the wavy surface topology for increased contact area. By merging these functions into one process step, the manufacturing complexity is minimized while achieving multiple beneficial effects.
Solution Approach 2:
The stressor layer performs multiple functions: it provides compressive or tensile stress to enhance dopant activation, acts as a source of dopants during subsequent annealing processes, and creates the wavy surface morphology that increases contact area. This multi-functionality reduces the need for separate processing steps, thereby managing manufacturing complexity while achieving improved device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The embedded stressor improves dopant activation and reduces contact resistance by increasing the contact area between the source/drain contact plugs and the underlying regions, enhancing the performance of FinFETs.
Implementation Method 1
an embedded stressor in the source/drain region with a wavy top surface, achieved through a multi-step epitaxy process, increases the contact area and reduces contact resistance by incorporating a higher dopant concentration and stressor layer that enhances dopant activation and stress distribution
Implementation Method 2
growing epitaxy regions starting from the recesses
Data Source
AI summary
A method includes forming a semiconductor fin, forming a gate stack on the semiconductor fin, and a gate spacer on a sidewall of the gate stack. The method further includes recessing the semiconductor fin to form a recess, performing a first epitaxy process to grow a first epitaxy semiconductor layer in the recess, wherein the first epitaxy semiconductor layer, and performing a second epitaxy process to grow an embedded stressor extending into the recess. The embedded stressor has a top portion higher than a top surface of the semiconductor fin, with the top portion having a first sidewall contacting a second sidewall of the gate spacer, and with the sidewall having a bottom end level with the top surface of the semiconductor fin. The embedded spacer has a bottom portion lower than the top surface of the semiconductor fin.