Way Enable Table for Multi-Threaded Cache Power Reduction
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Solution Overview
Problem
In multi-threaded processors, n-way set associative caches are power and data inefficient due to the need to power up all ways when reading data, even though only relevant data for the current thread is needed, leading to unnecessary power consumption and retrieval of irrelevant data from other threads.
Innovation Solution
A way enable table is introduced, which stores thread IDs for each cache entry, allowing only relevant ways in the cache to be powered up during data access by comparing the current thread ID with stored IDs, thereby enabling or disabling cache ways based on matching thread IDs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If all ways in the cache are powered up to read data, then data access speed is improved, but power consumption increases and irrelevant data from other threads is retrieved
Solution Approach 1:
The patent applies preliminary action by comparing the current thread ID with stored thread IDs in the way enable table before actually reading data from the cache. This pre-comparison step identifies which cache ways contain relevant data for the current thread, allowing the system to power up only those specific ways before the read operation, thus avoiding unnecessary power consumption from activating all ways while still maintaining fast access speed for relevant data.
2Reliability
If all ways in the cache are read to ensure data is found, then data retrieval completeness is improved, but data efficiency deteriorates due to retrieval of irrelevant data
Solution Approach 1:
The patent uses preliminary action by performing a thread ID comparison in the way enable table before reading cache data. This pre-filtering step identifies which cache ways contain data relevant to the current thread, allowing the system to read only from those specific ways. This ensures that all relevant data is retrieved while avoiding the retrieval of irrelevant data from other threads, thus maintaining data retrieval completeness while improving data efficiency.
3Loss of information
If thread ID storage is added to each cache entry, then data efficiency is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by separating the thread ID storage function from the main cache data structure. Instead of adding thread ID fields to every cache entry, the invention creates a separate way enable table that stores thread IDs indexed by cache way and set. This segmentation allows the cache to maintain its original simple structure while adding thread identification capability through an external lookup table, thus improving data efficiency without significantly increasing cache structure complexity.
Data Source
AI summary
Cache operation in a multi-threaded processor uses a small memory structure referred to as a way enable table that stores an index to an n-way set associative cache. The way enable table includes one entry for each entry in the n-way set associative cache and each entry in the way enable table is arranged to store a thread ID. The thread ID in an entry in the way enable table is the ID of the thread associated with a data item stored in the corresponding entry in the n-way set associative cache. Prior to reading entries from the n-way set associative cache identified by an index parameter, the ways in the cache are selective enabled based on a comparison of the current thread ID and the thread IDs stored in entries in the way enable table which are identified by the same index parameter.