Way Prediction Circuit for Cache Memory Power Reduction
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Solution Overview
Problem
Accessing a cache memory device in processors consumes significant power due to the need to activate all drivers and perform tag lookup operations, even though only a single cache line is accessed, leading to inefficient power usage.
Innovation Solution
A cache memory device with a cache circuit and a way prediction circuit that generates a cache hit signal and performs cache access operations based on candidate ways predicted using accumulation information from previous operations, reducing unnecessary power consumption by selectively activating only necessary ways.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all drivers corresponding to multiple ways are enabled to drive the data array to the multiplexer, then the cache can handle any possible access pattern, but power consumption increases significantly
Solution Approach 1:
The patent applies preliminary action by predicting which ways will be accessed before the actual cache access occurs. The way prediction circuit uses accumulation information from previous cache operations to generate candidate way signals in advance, allowing the system to pre-configure which drivers need to be activated, thereby avoiding the activation of all drivers and reducing power consumption while maintaining the ability to handle various access patterns.
2Speed
If tag lookup operations are performed for all ways in parallel, then the cache can identify the correct cache line quickly, but power consumption increases due to activating unnecessary ways
Solution Approach 1:
The way prediction circuit performs preliminary action by predicting candidate ways before the actual cache access. This allows the system to limit tag lookup operations to only the predicted candidate ways rather than all ways, maintaining fast access speed for the actual data while reducing power consumption by avoiding unnecessary tag comparisons in non-candidate ways.
Solution Approach 2:
The patent applies partial action by performing tag lookup operations on a subset of ways (candidate ways) rather than all ways. The way prediction circuit generates a limited set of candidate ways that are likely to contain the accessed data, and tag lookup is performed only on these partial ways, reducing the total number of operations and power consumption while still achieving the correct data retrieval.
3Quantity of substance
If only a single cache line is accessed, then the actual data transfer is minimal, but power consumption remains high due to activating all drivers and performing full tag lookup
Solution Approach 1:
The patent applies partial action by activating only the drivers corresponding to predicted candidate ways rather than all drivers. Since only a single cache line needs to be accessed, the way prediction circuit limits driver activation to a small subset of candidate ways, and further refines this to the single correct way through tag lookup, thereby matching the actual data transfer volume with the activation scope and significantly reducing power consumption.
Data Source
AI summary
A cache memory device includes a cache circuit and a way prediction circuit. The cache circuit generates a cache hit signal indicating whether target data corresponding to an access address are stored in cache lines and performs a current cache access operation primarily with respect to candidate ways based on a candidate way signal indicating the candidate ways in a way prediction mode. The way prediction circuit stores accumulation information by accumulating a cache hit result indicating whether the target data are stored in one of ways and a way prediction hit result indicating whether the target data are stored in one of the candidate ways based on the cache hit signal provided during previous cache access operations. The way prediction circuit generates the candidate way signal by determining the candidate ways for the current cache access operation based on the accumulation information in the way prediction mode.