Write Timing Adjustment via WCDR Phase Correlation
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Solution Overview
Problem
As operating frequencies increase, memory devices face challenges in accurately sampling data due to signal attenuation caused by temperature and jitter, leading to poor data recovery, necessitating a method to adjust write timing effectively.
Innovation Solution
The implementation of a Write Clock Data Recovery (WCDR) mode of operation, which includes an address/control bus, a WCDR signal bus, and a phase correlation module to detect and adjust phase shifts between data and clock signals, ensuring proper alignment and sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If operating frequency is increased to transmit data more rapidly, then productivity is improved, but data signal integrity deteriorates due to signal attenuation and timing errors
Solution Approach 1:
The patent applies preliminary action by performing write timing adjustment before actual data writing occurs. The system adjusts the write timing delay based on previously detected phase shifts between data and clock signals, so that when data is written, the timing is already optimized for proper sampling despite signal attenuation from high-frequency operation
Solution Approach 2:
The patent implements feedback by continuously monitoring the phase relationship between data signals and clock signals, detecting write timing errors, and using this information to adjust the write timing delay. This closed-loop feedback mechanism enables the system to compensate for signal attenuation and maintain data integrity at high operating frequencies
2Measurement precision
If write timing is adjusted to compensate for signal attenuation, then data recovery accuracy is improved, but device complexity increases due to additional timing adjustment mechanisms
Solution Approach 1:
The patent applies universality by designing a timing adjustment mechanism that serves multiple functions: it compensates for signal attenuation, corrects phase shifts, and maintains proper sampling timing. This multi-functional approach improves data recovery accuracy without proportionally increasing device complexity, as the same mechanism addresses multiple timing-related issues
Data Source
AI summary
Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data.